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| 8 Bit Microcontroller TLCS-870/C Series TMP86FS64FG TMP86FS64FG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 Revision History Date 2005/12/27 2006/2/6 2006/6/29 2006/8/22 Revision 1 2 3 4 First Release Contents Revised Periodical updating.No change in contents. Contents Revised Table of Contents TMP86FS64FG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 6 2. Operational Descriptions 2.1 CPU Core Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Address Map............................................................................................................................. 11 Program Memory (Flash) ........................................................................................................................ 12 Data Memory (RAM) ............................................................................................................................... 12 Clock Generator...................................................................................................................................... 13 Timing Generator .................................................................................................................................... 14 Operating Modes .................................................................................................................................... 16 Single-Clock Mode Dual-Clock Mode STOP Mode Operation Mode Transition Timing Generator Configuration Machine Cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.3.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 21 STOP Mode IDLE1/2 and SLEEP1/2 Modes IDLE0 and SLEEP0 Modes SLOW Mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 External Reset Input ............................................................................................................................... 36 Address-Trap-Reset ............................................................................................................................... 37 Watchdog Timer Reset ........................................................................................................................... 37 System Clock Reset ............................................................................................................................... 37 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Interrupt acceptance processing is packaged as follows........................................................................ 43 Saving/restoring general-purpose registers ............................................................................................ 44 Interrupt return ........................................................................................................................................ 46 Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 40 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 41 3.4.1 3.4.2 3.4.3 3.5.1 3.4.2.1 3.4.2.2 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Address error detection .......................................................................................................................... 47 i 3.6 3.7 3.8 3.5.2 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Debugging .............................................................................................................................................. 47 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P8 (P87 to P80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P9 (P97 to P90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port PA (PA7 to PA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port PB (PB7 to PB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 59 60 61 62 64 65 67 69 70 71 72 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 74 75 76 76 77 6.3 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 78 78 78 79 6.3.1 6.3.2 6.3.3 6.3.4 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Configuration .......................................................................................................................................... 81 Control .................................................................................................................................................... 81 Function .................................................................................................................................................. 82 Configuration .......................................................................................................................................... 83 Control .................................................................................................................................................... 83 7.1.1 7.1.2 7.1.3 7.2.1 7.2.2 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ii 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Timer mode............................................................................................................................................. 88 External Trigger Timer Mode .................................................................................................................. 90 Event Counter Mode ............................................................................................................................... 92 Window Mode ......................................................................................................................................... 93 Pulse Width Measurement Mode............................................................................................................ 94 Programmable Pulse Generate (PPG) Output Mode ............................................................................. 97 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 9. 16-Bit Timer/Counter2 (TC2) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Timer mode........................................................................................................................................... 103 Event counter mode.............................................................................................................................. 105 Window mode ....................................................................................................................................... 105 9.3.1 9.3.2 9.3.3 10. 8-Bit TimerCounter 3 (TC3) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.3.1 Timer mode......................................................................................................................................... 109 Figure 10-3 .................................................................................................................................................... 111 10.3.3 Capture Mode ..................................................................................................................................... 112 11. 8-Bit TimerCounter 4 (TC4) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Timer Mode......................................................................................................................................... Event Counter Mode ........................................................................................................................... Programmable Divider Output (PDO) Mode ....................................................................................... Pulse Width Modulation (PWM) Output Mode .................................................................................... 116 117 118 119 11.3.1 11.3.2 11.3.3 11.3.4 12. 8-Bit TimerCounter 5 (TC5) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Timer Mode......................................................................................................................................... Event Counter Mode ........................................................................................................................... Programmable Divider Output (PDO) Mode ....................................................................................... Pulse Width Modulation (PWM) Output Mode .................................................................................... 124 125 126 127 12.3.1 12.3.2 12.3.3 12.3.4 iii 13. 8-Bit TimerCounter 6 (TC6) 13.1 13.2 13.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Timer Mode......................................................................................................................................... Event Counter Mode ........................................................................................................................... Programmable Divider Output (PDO) Mode ....................................................................................... Pulse Width Modulation (PWM) Output Mode .................................................................................... 132 133 134 135 13.3.1 13.3.2 13.3.3 13.3.4 14. Asynchronous Serial interface (UART ) 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared (IrDA) Data Format Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 143 Data Receive Operation ..................................................................................................................... 143 Parity Error........................................................................................................................................ Framing Error.................................................................................................................................... Overrun Error .................................................................................................................................... Receive Data Buffer Full................................................................................................................... Transmit Data Buffer Empty ............................................................................................................. Transmit End Flag ............................................................................................................................ 144 144 144 145 145 146 137 138 140 141 142 142 143 143 143 14.9.1 14.9.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.10.1 14.10.2 14.10.3 14.10.4 14.10.5 14.10.6 15. Synchronous Serial Interface (SIO1) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Clock source ....................................................................................................................................... 149 Shift edge............................................................................................................................................ 151 Leading edge Trailing edge Internal clock External clock 15.3.1.1 15.3.1.2 15.3.2.1 15.3.2.2 15.3.1 15.3.2 15.4 15.5 15.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4-bit and 8-bit transfer modes ............................................................................................................. 152 4-bit and 8-bit receive modes ............................................................................................................. 154 8-bit transfer / receive mode ............................................................................................................... 155 15.6.1 15.6.2 15.6.3 16. Synchronous Serial Interface (SIO2) 16.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 iv 16.2 16.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Clock source ....................................................................................................................................... 161 Shift edge............................................................................................................................................ 163 Leading edge Trailing edge Internal clock External clock 16.3.1.1 16.3.1.2 16.3.2.1 16.3.2.2 16.3.1 16.3.2 16.4 16.5 16.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4-bit and 8-bit transfer modes ............................................................................................................. 164 4-bit and 8-bit receive modes ............................................................................................................. 166 8-bit transfer / receive mode ............................................................................................................... 167 16.6.1 16.6.2 16.6.3 17. 10-bit AD Converter (ADC) 17.1 17.2 17.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Software Start Mode ........................................................................................................................... 175 Repeat Mode ...................................................................................................................................... 175 Register Setting ................................................................................................................................ 176 17.4 17.5 17.6 17.3.1 17.3.2 17.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 178 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Analog input pin voltage range ........................................................................................................... 179 Analog input shared pins .................................................................................................................... 179 Noise Countermeasure ....................................................................................................................... 179 17.6.1 17.6.2 17.6.3 18. Key-on Wakeup (KWU) 18.1 18.2 18.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 19. Flash Memory 19.1 19.2 Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Byte Program ...................................................................................................................................... Sector Erase (4-kbyte Erase) ............................................................................................................. Chip Erase (All Erase) ........................................................................................................................ Product ID Entry ................................................................................................................................. Product ID Exit .................................................................................................................................... Read Protect ....................................................................................................................................... 185 185 186 186 186 186 Flash Memory Command Sequence Execution Control (FLSCR 19.3 19.4 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 Toggle Bit (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Access to the Flash Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Flash Memory Control in the Serial PROM Mode............................................................................... 188 Flash Memory Control in the MCU mode............................................................................................ 190 How to write to the flash memory by executing a user write control program in the RAM area (in the MCU mode) How to write to the flash memory by executing the control program in the RAM area (in the RAM loader mode within the serial PROM mode) 19.4.1 19.4.2 19.4.1.1 19.4.2.1 v 20. Serial PROM Mode 20.1 20.2 20.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Serial PROM Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Serial PROM Mode Control Pins ........................................................................................................ Pin Function........................................................................................................................................ Example Connection for On-Board Writing......................................................................................... Activating the Serial PROM Mode ...................................................................................................... 194 194 195 196 20.4 20.5 20.6 20.3.1 20.3.2 20.3.3 20.3.4 Interface Specifications for UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Flash Memory Erasing Mode (Operating command: F0H) ................................................................. Flash Memory Writing Mode (Operation command: 30H) .................................................................. RAM Loader Mode (Operation Command: 60H) ................................................................................ Flash Memory SUM Output Mode (Operation Command: 90H) ......................................................... Product ID Code Output Mode (Operation Command: C0H).............................................................. Flash Memory Status Output Mode (Operation Command: C3H) ...................................................... Flash Memory Read Protection Setting Mode (Operation Command: FAH) ...................................... 201 203 206 208 209 211 212 20.7 20.8 20.6.1 20.6.2 20.6.3 20.6.4 20.6.5 20.6.6 20.6.7 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Checksum (SUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Calculation Method ............................................................................................................................. 214 Calculation data .................................................................................................................................. 215 20.9 Intel Hex Format (Binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 20.10 Passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 20.10.1 20.10.2 20.10.3 Password String................................................................................................................................ 217 Handling of Password Error .............................................................................................................. 217 Password Management during Program Development .................................................................... 217 20.8.1 20.8.2 20.11 20.12 20.13 20.14 20.15 20.16 Product ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Status Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Erasure Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Input Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 218 220 220 222 223 21. Input/Output Circuitry 21.1 21.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 22. Electrical Characteristics 22.1 22.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 MCU mode (Flash Programming or erasing) ..................................................................................... 228 MCU mode (Except Flash Programming or erasing) ......................................................................... 228 Serial PROM mode ............................................................................................................................. 229 22.3 22.4 22.5 22.6 22.2.1 22.2.2 22.2.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write/Retention Characteristics .......................................................................................................... 234 230 232 234 234 22.6.1 vi 22.7 22.8 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 23. Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vii viii TMP86FS64FG CMOS 8-Bit Microcontroller TMP86FS64FG The TMP86FS64FG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of Flash Memory. It is pin-compatible with the TMP86CS64AFG (Mask ROM version). The TMP86FS64FG can realize operations equivalent to those of the TMP86CS64AFG by programming the on-chip Flash Memory. Product No. TMP86FS64FG ROM (FLASH) 61440 bytes RAM 2048 bytes Package P-QFP100-1420-0.65A MASK ROM MCU TMP86CS64AFG Emulation Chip TMP86C964XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 21interrupt sources (External : 6 Internal : 15) 3. Input / Output ports (91 pins) Large current output: 16pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 16-bit timer counter: 1 ch - Timer, Event counter, Window modes 8. 8-bit timer counter : 1 ch This product uses the Super Flash technology under the licence of Silicon Storage Technology, Inc. Super Flash is registered trademark of Silicon Storage Technology, Inc. 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86FS64FG - Timer, Event counter, Capture modes 9. 8-bit timer counter : 3 ch - Timer, Event counter, Pulse width modulation (PWM) output, Programmable divider output (PDO) modes 10. 8-bit UART : 1 ch 11. 8-bit SIO: 2 ch 12. 10-bit successive approximation type AD converter - Analog input: 16 ch 13. Key-on wakeup : 4 ch 14. Clock operation Single clock mode Dual clock mode 15. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Release by Page 2 1.2 Pin Assignment P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P50 P51 P52 P53 P54 P55 P56 P57 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (STOP/INT5) P20 (PWM4/PDO4/TC4) P30 (PWM5/PDO5/TC5) P31 (PWM6/PDO6/TC6) P32 (SCK1) P33 (SI1) P34 (SO1) P35 (SI2) P36 (SO2) P37 (SCK2) P40 (RXD1) P41 (TXD1) P42 P43 (BOOT/RXD2) P44 (TXD2) P45 (TC3/INT3) P46 (INT4) P47 (AIN0) P60 (AIN1) P61 (AIN2) P62 (AIN3) P63 (AIN4) P64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P83 P82 P81 P80 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P15 (TC2) P14 (PPG) P13 (DVO) P12 (INT2/TC1) P11 (INT1) P10 (INT0) AVSS AVDD VAREF P77 (AIN15/STOP5) P76 (AIN14/STOP4) P75 (AIN13/STOP3) P74 (AIN12/STOP2) P73 (AIN11) P72 (AIN10) P71 (AIN9) P70 (AIN8) P67 (AIN7) P66 (AIN6) P65 (AIN5) TMP86FS64FG 1.3 Block Diagram TMP86FS64FG 1.3 Block Diagram Page 4 TMP86FS64FG Figure 1-2 Block Diagram Page 5 1.4 Pin Names and Functions TMP86FS64FG 1.4 Pin Names and Functions The TMP86FS64FG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/4) Pin Name P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 TC2 P14 PPG Pin Number 60 59 58 57 56 55 54 53 52 51 50 Input/Output IO IO IO IO IO IO IO IO IO IO IO I IO O IO O IO I I IO I IO I IO O IO I IO I I IO O IO I IO O IO I IO IO PORT07 PORT06 PORT05 PORT04 PORT03 PORT02 PORT01 PORT00 PORT17 PORT16 PORT15 TC2 input PORT14 PPG output PORT13 Divider Output PORT12 External interrupt 2 input TC1 input PORT11 External interrupt 1 input PORT10 External interrupt 0 input Functions 49 P13 DVO 48 P12 INT2 TC1 P11 INT1 P10 INT0 47 46 45 P22 XTOUT P21 XTIN P20 INT5 STOP 7 PORT22 Low frequency OSC output pin PORT21 Low frequency OSC input pin PORT20 External interrupt 5 input STOP mode release input PORT37 Serial Data Output 2 PORT36 Serial Data Input 2 PORT35 Serial Data Output 1 PORT34 Serial Data Input 1 PORT33 Serial Clock I/O 1 6 9 P37 SO2 P36 SI2 P35 SO1 P34 SI1 P33 SCK1 17 16 15 14 13 Page 6 TMP86FS64FG Table 1-1 Pin Names and Functions(2/4) Pin Name P32 TC6 PWM6/PDO6 Pin Number Input/Output IO I O IO I O IO I O IO I IO I I IO O IO I I IO IO O IO I IO IO IO IO IO IO IO IO IO IO IO I IO I IO I IO I IO I IO I PORT32 TC6 input PWM6/PDO6 output PORT31 TC5 input PWM5/PDO5 output PORT30 TC4 input PWM4/PDO4 output PORT47 External interrupt 4 input PORT46 External interrupt 3 input TC3 pin input PORT45 UART data output 2 Functions 12 P31 TC5 PWM5/PDO5 11 P30 TC4 PWM4/PDO4 10 P47 INT4 P46 INT3 TC3 P45 TXD2 P44 RXD2 BOOT P43 P42 TXD1 P41 RXD1 P40 SCK2 25 24 23 22 PORT44 UART data input 2 Serial PROM mode control input PORT43 PORT42 UART data output 1 PORT41 UART data input 1 PORT40 Serial Clock I/O 2 PORT57 PORT56 PORT55 PORT54 PORT53 PORT52 PORT51 PORT50 PORT67 Analog Input7 PORT66 Analog Input6 PORT65 Analog Input5 PORT64 Analog Input4 PORT63 Analog Input3 PORT62 Analog Input2 21 20 19 18 100 99 98 97 96 95 94 93 33 P57 P56 P55 P54 P53 P52 P51 P50 P67 AIN7 P66 AIN6 P65 AIN5 P64 AIN4 P63 AIN3 P62 AIN2 32 31 30 29 28 Page 7 1.4 Pin Names and Functions TMP86FS64FG Table 1-1 Pin Names and Functions(3/4) Pin Name P61 AIN1 P60 AIN0 P77 AIN15 STOP5 P76 AIN14 STOP4 P75 AIN13 STOP3 P74 AIN12 STOP2 P73 AIN11 P72 AIN10 P71 AIN9 P70 AIN8 P87 P86 P85 P84 P83 P82 P81 P80 P97 P96 P95 P94 P93 P92 P91 P90 PA7 PA6 Pin Number 27 Input/Output IO I IO I IO I I IO I I IO I I IO I I IO I IO I IO I IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PORT61 Analog Input1 PORT60 Analog Input0 PORT77 Analog Input15 STOP5 input PORT76 Analog Input14 STOP4 input PORT75 Analog Input13 STOP3 input PORT74 Analog Input12 STOP2 input PORT73 Analog Input11 PORT72 Analog Input10 PORT71 Analog Input9 PORT70 Analog Input8 PORT87 PORT86 PORT85 PORT84 PORT83 PORT82 PORT81 PORT80 PORT97 PORT96 PORT95 PORT94 PORT93 PORT92 PORT91 PORT90 PORTA7 PORTA6 Functions 26 41 40 39 38 37 36 35 34 84 83 82 81 80 79 78 77 92 91 90 89 88 87 86 85 68 67 Page 8 TMP86FS64FG Table 1-1 Pin Names and Functions(4/4) Pin Name PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XIN XOUT RESET Pin Number 66 65 64 63 62 61 76 75 74 73 72 71 70 69 2 3 8 4 42 43 44 5 1 Input/Output IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I I I I I I I PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Functions High frequency OSC input pin High frequency OSC output pin RESET input TEST pin (Fix to Low level) Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply Analog Power Supply VDD pin GND pin TEST VAREF AVDD AVSS VDD VSS Page 9 1.4 Pin Names and Functions TMP86FS64FG Page 10 TMP86FS64FG 2. Operational Descriptions 2.1 CPU Core Function The CPU core consists of a CPU, a system clock controller and an interrupt controller. This chapter provides descriptions of the CPU core, the program memory, the data memory and the reset circuit. 2.1.1 Memory Address Map TMP86FS64FG memory consists of RAM and Special Function Register (SFR), which are mapped to a 64 Kbyte address space. The TMP86FS64FG memory consists of Flash, RAM, Special Function Register (SFR) and Data Buffer Resister (DBR), which are mapped to a 64 kbyte address space. Figure 2-1 shows the TMP86FS64FG memory address map. SFR 0000H 003FH 0040H 64 bytes SFR: RAM 2048 bytes RAM: 083FH Special function register I/O port Peripheral hardware control register Peripheral hardware status register System control register Program status word Random access memory Data memory Stack 0F80H DBR 128 bytes 0FFFH DBR: Data buffer register Peripheral hardware control register Peripheral hardware status register 1000H Flash: Program memory Flash FFC0H FFDFH FFE0H FFFFH 61440 bytes Vector table for vector call instructions (32 bytes) Instruction vector table (32 bytes) Figure 2-1 Memory Address Map Page 11 2. Operational Descriptions 2.1 CPU Core Function TMP86FS64FG 2.1.2 Program Memory (Flash) TMP86FS64FG incorporates the 61440-byte (addresses from 1000H through FFFFH) program memory (Flash). 2.1.3 Data Memory (RAM) TMP86FS64FG incorporates the 2048-byte (addresses from 0040H through 083FH) RAM. Since the address space from 0040H through 00FFH within the on-chip RAM can be accessed directly, it can be accessed by instructions to shorten the processing time. Perform initial setting through an initialize routine since the contents of the data memory become don't cares at power-up. Example :Clearing RAM of TMP86FS64FG LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC,07FFH (HL), A HL BC F, SRAMCLR : Sets the start address : Sets the initialization data (00H) : Sets the number of bytes (-1) Page 12 TMP86FS64FG 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator and a operating mode controller. Divider control Timing generator register control register CGCR TBTCR Clock generator XIN High-frequency clock oscillator XOUT XTIN Low-frequency clock oscillator XTOUT Oscillate/Stop control fs System clock fc Operating mode controller Timing generator 0038H SYSCR1 0039H SYSCR2 0030H 0036H System control register Figure 2-2 System Clock Controller 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks to be supplied to the CPU core and peripheral hardware. The clock generator contains two oscillators used for the high- and low-frequency clocks. Power consumption can be reduced by the low-speed operation with the low-frequency clock, which is switched by the operating mode controller. The high-frequency clock (fc) or low-frequency clock (fs) can be obtained easily by connecting a resonator between the XIN and XOUT pins, or XTIN and XTOUT pins, respectively. The clock can be supplied from an external oscillator. In this case, supply the clock via the XIN or XTIN pin, and leave the XOUT or XTOUT pins unconnected. High-frequency clock XIN XOUT XIN XOUT XTIN Low-frequency clock XTOUT XTIN XTOUT (Unconnected) (Unconnected) (a) Crystal or ceramic resonator (b) External oscillator (c) Crystal resonator (d) External oscillator Figure 2-3 Example Resonator Connection Note:The hardware feature does not provide the function to monitor externally the basic clock directly. However, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by programming to output a fixed-frequency pulse (i.e., clock output) to a port and monitoring the pulse. For the system to require the adjustment of the oscillation frequency, the adjustment program must be created beforehand. Page 13 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG 2.2.2 Timing Generator The timing generator generates various types of system clocks which are supplied to the CPU core or peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generating the main system clock 2. Generating the divider output (DVO) pulses 3. Generating the source clocks for the time base timer 4. Generating the source clocks for the watchdog timer 5. Generating the internal source clocks for the TimerCounter 6. Generating the warm-up clocks upon exit from the STOP mode 2.2.2.1 Timing Generator Configuration The timing generator consists of a 3-stage prescaler, a 21-stage divider, a main system clock generator and a machine cycle counter. Either the clock fc/4 output from the 2nd stage or the clock fc/8 output from the 3rd stage can be selected as the clock input to the 1st stage of the divider by CGCR Note: TBTCR Table 2-1 Divider Output Divider Output DV1CK = 0 DV1G fc/23 DV2G fc/24 DV3G fc/25 DV4 fc/26 DV5 fc/27 DV1G fc/24 DV2G fc/25 DV1CK = 1 DV3G fc/26 DV4 fc/27 DV5 fc/28 Table 2-2 Input Clock to 7th Stage of the Divider [Hz] NORMAL1, IDLE1 mode DV7CK = 0 DV1CK = 0 fc/28 DV1CK = 1 fc/29 NORMAL2, IDLE2 mode (SYSCK=0) DV7CK = 0 DV7CK = 1 DV1CK = 0 fc/28 DV1CK = 1 fc/29 fs SLOW1/2, SLEEP1/2 mode (SYSCK = 1) fs Note 1: Do not set TBTCR Page 14 TMP86FS64FG Main system clock generator SYSCR2 fc or fs Machine cycle counter DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 DV10 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV20 Low-frequency clock fc Selector Selector DV21 DV11 High-frequency clock fc 012 S A Y B Divider 123456 S A Y B Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S Selector B0 B1 A0 Y0 Warm-up A1 Y1 controller Watchdog timer TimerCounter, time base timer, divider output, etc. Figure 2-4 Timing Generator Configuration Table 2-3 Division Ratio of the Divider DV7CK = 0 DV1CK = 0 DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 DV10 DV11 fc/23 fc/24 fc/25 fc/26 fc/27 fc/28 fc/29 fc/210 fc/211 fc/212 fc/213 DV1CK = 1 fc/24 fc/25 fc/26 fc/27 fc/28 fc/29 fc/210 fc/211 fc/212 fc/213 fc/214 DV7CK = 1 DV1CK = 0 fc/23 fc/24 fc/25 fc/26 fc/27 fc/28 fs/2 fs/22 fs/23 fs/24 fs/25 DV1CK = 1 fc/24 fc/25 fc/26 fc/27 fc/28 fc/29 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV19 DV20 DV21 DV7CK = 0 DV1CK = 0 fc/214 fc/215 fc/216 fc/217 fc/218 fc/219 fc/220 fc/221 fc/222 fc/223 DV1CK = 1 fc/215 fc/216 fc/217 fc/218 fc/219 fc/220 fc/221 fc/222 fc/223 fc/224 DV7CK = 1 DV1CK = 0 DV1CK = 1 fs/26 fs/27 fs/28 fs/29 fs/210 fs/211 fs/212 fs/213 fs/214 fs/215 Divider Control Register CGCR (0030H) 7 "0" 6 "0" 5 DV1CK 4 "0" 3 "0" 2 "0" 1 "0" 0 "0" (Initial value: **0* ****) DV1CK Selection of the input clock to the 1st stage of the divider [Hz] 0: 1: fc/4 fc/8 R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: The bit 4 and 3 are read as a don't care when the read instruction is executed to CGCR. Page 15 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG Note 3: 0 must be written to the bit 7, 6, 4 through 0 of CGCR. Timing Generator Control Resister 7 TBTCR (0036H) (DVOE N) 6 5 4 DV7CK 3 (TBTE N) 2 1 (TBTCK) 0 (Initial value: 0000 0000) (DVOCK) DV7CK Selection of the input clock to the 7th stage of the divider 0: fc/28[Hz] 1: fs R/W Note 1: Do not set DV7CK to 1 in the single-clock mode. Note 2: Do not set DV7CK to 1 until the low-frequency clock oscillation is stabilized. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In the SLOW 1/2 or SLEEP1/2 mode, fs is input to the 7th stage of the divider regardless of DV7CK setting. Note 5: When the STOP mode is entered from the NORMAL1/2 mode, the output of the 6th stage of the divider is input to the 7th stage of the divider during warm up after exiting from the STOP mode regardless of DV7CK setting. 2.2.2.2 Machine Cycle The instruction execution and peripheral hardware operation are synchronized with the system clock. The minimum instruction execution unit is called a "machine cycle". There are 10 types of instructions for TLCS-870/C Series, which are 1-cycle instructions to be executed within 1-cycle through 10-cycle instructions to be executed within ten cycles. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operating Modes The operating mode controller starts and stops the oscillators for the high-frequency and low-frequency clocks, and switches the main system clock. The device has the single-clock, dual-clock and STOP modes, which can be controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition. Page 16 TMP86FS64FG 2.2.3.1 Single-Clock Mode In the single-clock mode, only the oscillator for high-frequency clock is used. The P21(XTIN) and P22 (XTOUT) pins for the low-frequency clock can be used as usual I/O ports. Since the main system clock is generated from the high-frequency clock, the machine cycle time becomes 4/fc [s] in the single-clock mode. (1) NORMAL1 mode In the NORMAL1 mode, the CPU core and on-chip peripherals operate using the high-frequency clock. After reset is released, NOMAL1 mode is entered. (2) IDLE1 mode In the IDLE1 mode, the CPU and watchdog timer are halted, and on-chip peripherals are clocked by the high-frequency clock. To enter the IDLE1 mode, set IDEL in the system control register 2 (SYSCR2) to 1. The IDLE1 mode is exited by the interrupt from the on-chip peripherals or external interrupts, and returned to the NORMAL1 mode. When the IMF (interrupt master enable flag) is set to 1 (interrupt enable), the normal operation is performed after the interrupt processing is completed. When the IMF is set to 0 (interrupt disable), program execution resumes with the instruction immediately following the instruction that activated the IDLE1 mode. (3) IDLE0 mode In the IDLE0 mode, the CPU and on-chip peripherals are halted except oscillator and TBT. The IDEL0 mode is entered by setting the system control register SYSCR2 2.2.3.2 Dual-Clock Mode In the dual-clock mode, two oscillators for high-frequency and low-frequency are used. The P21 (XTIN) and P22 (XTOUT) pins are used for the low-frequency clock pins. (In the dual-clock mode, these pins can not be used as I/O ports.) The main system clock is generated by the high-frequency clock in the NORMAL2 and IDLE2 modes, and the low-frequency clock in the SLOW1/2 and SLEEP1/2 modes. Therefore, the machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s @ fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C series is put in the single-clock mode during reset. To use the dual-clock mode, oscillate the low-frequency clock at the top of the program. (1) NORMAL2 Mode The CPU core operates with high-frequency clock. On-chip peripherals operate with high- and low-frequency clocks. Page 17 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG (2) SLOW2 Mode The CPU core operates with low-frequency clock. Switching from NORMAL2 to SLOW2, and vise-versa is programmed in SYSCR2 (3) SLOW1 Mode Power dissipation can be reduced by stopping high-frequency clock oscillation, and operating the CPU core and on-chip peripherals with low-frequency clock. Switching from SLOW1 to SLOW2, and vise-versa is programmed in SYSCR2 (4) IDLE2 Mode The CPU and watchdog timer are halted, and on-chip peripherals are operated with the high- and low-frequency clocks. Entering and exiting the IDLE2 mode is the same as for the IDLE1 mode. After exiting the IDLE2 mode, the CPU returns to the NORMAL2 mode. (5) SLEEP1 Mode The CPU and watchdog timer are halted, and on-chip peripherals are operated with the low-frequency clock. Entering and exiting the SLEEP1 mode is the same as for the IDLE1 mode. After exiting the SLEEP1 mode, th CPU returns to the SLOW1 mode. High-frequency clock oscillation is stopped. In the SLOW1 and SLEEP1 modes, output from the 1st to 6th stages is stopped. (6) SLEEP2 Mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The SLEEP2 mode is the same as the SLOW2 mode except that high-frequency clock is activated. (7) SLEEP0 Mode The CPU and on-chip peripherals are halted except oscillator and TBT. The SLEEP0 mode is entered by setting the system control register SYSCR2 Page 18 TMP86FS64FG 2.2.3.3 STOP Mode In the STOP mode, all system operations including oscillators are halted, and the internal conditions immediately before the halt are retained with low-power dissipation. The STOP mode is entered by setting the system control register 1, and exited with the STOP pin input. After the warm-up period time has expired, the CPU returns to the mode it was before entering the STOP mode, and program execution resumes with the instruction immediately following the instruction that activated the STOP mode. 2.2.3.4 Operation Mode Transition IDLE0 mode SYSCR2 RESET Reset released SYSCR1 STOP pin input SYSCR2 IDLE2 mode STOP pin input SYSCR2 STOP SYSCR1 STOP pin input (Note 2) SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL mode: SLOW1 and SLOW2 are called SLOW mode: IDLE0 and IDLE1 and IDLE2 are called IDLE mode: SLEEP0, SLEEP1 and SLEEP2 are called SLEEP mode. Note 2: This mode is exited at the falling edge of the source clock selected in TBTCR Figure 2-6 Operating Mode Transition Page 19 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG Table 2-4 Operating Mode and Conditions Oscillator Operating Mode High-freq. RESET NORMAL1 SingleClock Oscillation IDLE1 IDLE0 STOP NORMAL2 IDLE2 Oscillation SLOW2 Dual-Clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Halt Halt Halt Oscillation Operate with Low-freq. Halt Operate with Low-freq. Operate 4/fs [s] Operate Stop Operate with High-freq. Halt Stop Halt Halt Halt Operate Low-freq. Reset Operate Operate 4/fc [s] Reset CPU Core TBT Other Peripherals Reset Machine Cycle Time 4/fc [s] Page 20 TMP86FS64FG 2.2.4 Operating Mode Control System Control Register 1 7 SYSCR1 (0038H) STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 "0" 0 (Initial value: 0000 00**) STOP STOP mode enter 0: CPU core and peripherals operate 1: CPU core and peripherals halt (Enter STOP mode) 0: Edge-sensitive (Exit at the rising edge of STOP pin) 1: Level-sensitive (Exit at the high level of STOP pin) 0: Return to NORMAL 1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output retained Return to NORMAL 1/2 mode DV1CK=0 DV1CK=1 3 x 217/fc 217/fc 3 x 215/fc 2 /fc 15 R/W RELM STOP mode exit method Operating mode after STOP mode Port output during STOP mode R/W RETM R/W OUTEN R/W Return to SLOW1 mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W WUT Warm-up time on exiting STOP mode [ns] 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 2 /fc 14 Note 1: To transit from the NOMAL mode to the STOP mode, set RETM to 0. To transit from the STOP mode to the NOMAL mode, set RETM to 1. Note 2: When exiting the STOP mode with the RESET pin input, the CPU returns to the NORMAL1 mode regardless of the RETM value. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: Bit 1 and 0 in SYSCR1 are read as don't cares. Note 5: When entering the STOP mode with OUTEN = 0, input value is fixed to 0. That may cause an external interrupt request to be set on falling edge. Note 6: To use the Key on wake-up is used, set RELM to 1. Note 7: The P20 pin is shared with the STOP pin. When the STOP mode is entered, output assumes the high-impedance state regardless of the OUTEN state. Note 8: Select the warm-up period time depending on the feature of the resonator to be used. Page 21 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG System Control Register 2 7 SYSCR2 (0039H) XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHAL T 1 0 (Initial value: 1000 *0**) XEN XTEN SYSCK IDLE High-frequency oscillator control Low-frequency oscillator control System clock select (write)/monitor (read) CPU and WDT control (IDLE1/2, SLEEP1/2 mode) TG control (IDLE0, SLEEP0 mode) 0: Stop oscillation 1: Continue or start oscillation 0: Stop oscillation 1: Continue or start oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW/SLEEP) 0: CPU, WDT enabled 1: CPU, WDT disabled (Enter IDLE1/2, SLEEP1/2 mode) 0: Clocking operation to all peripherals from TG 1: Stop the clocking operation to peripherals except TBT from TG (Enter IDLE0, SLEEP0 mode) R/W R/W TGHALT R/W Note 1: Reset is performed when both XEN and XTEN are cleared to 0, XEN is cleared to 0 with SYSCK = 0, or XTEN is cleared to 0 with SYSCK = 1. Note 2: WDT: watchdog timer, TG: timing generator, *: Don't care Note 3: When the bit 3, 1 or 0 of SYSCR2 is read, a don't care is read. Note 4: Do not set IDLE and TGHALT to 1 simultaneously. Note 5: Since the IDLE0/SLEEP0 mode is returned to the NORMAL1/SLOW1 mode by the asynchronous internal source clock specified in TBTCR Page 22 TMP86FS64FG 2.2.4.1 STOP Mode The STOP mode is controlled by the system control resister 1 (SYSCR1), STOP pin input and STOP5 to STOP2. The STOP pin is used as the P20 port and INT5 pin (external interrupt input 5). The STOP mode is entered by setting SYSCR1 Note 1: Unlike the key-on wake-up input pin, the STOP pin does not have the function to disable input. To use the STOP mode, the STOP pin must be used to exit the STOP mode. Note 2: During STOP period (from the start of the STOP mode to the end of warm-up period time), interrupt latches are set to 1 due to external interrupt signal changes, and interrupts may be accepted immediately after the STOP mode is exited. Therefore, disable interrupts before entering the STOP mode. Before enabling interrupts after the STOP mode is exited, clear unnecessary interrupt latches beforehand. (1) Level-sensitive exit mode (RELM = 1) In this mode, the STOP mode is exited by setting the STOP pin to high or STOP5 to STOP2 (can be specified to each bit in STOPCR) to low. This mode is used for capacitor back-up when the main power supply is cut off and long tern battery back-up. When the STOP pin input is set to high or STOP5 to STOP2 is set to low, executing an instruction to enter the STOP mode does not enter the STOP mode, but immediately starts the exit sequence (warm-up). When the STOP mode is entered in the level-sensitive exit mode, it is required to check that the STOP pin input is programmed to low and the STOP5 to STOP2 pin input is programmed to high by the following methods. 1. Testing the port condition. 2. Using the INT5 interrupt (an interrupt is generated at the falling edge of the INT5 pin input) Example 1 :Entering the STOP mode from the NORMAL mode by testing a port P20 LD SSTOPH: TEST JRS DI SET (SYSCR1) . 7 (SYSCR1), 01010000B (P2PRD) . 0 F, SSTOPH : IMF0 : Enters the STOP mode. : Sets the level-sensitive exit mode. : Wait state until the STOP pin input becomes low. Page 23 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG Example 2 :Entering the STOP mode from the NORMAL mode by the INT5 interrupt PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1) . 7 (P2PRD) . 0 F, SINT5 (SYSCR1), 01010000B : IMF0 : Enters the STOP mode. : To eliminate spurious noise, the STOP mode is not entered if the P20 port input is set to high. : Sets the level-sensitive exit mode. STOP pin VIH XOUT pin NORMAL mode STOP mode Detect the low level of the STOP pin input by programming and enter the STOP mode. Warm-up NORMAL mode Exit the STOP mode by hardware. Whenever the STOP pin input is set to high, the STOP mode is exited. Figure 2-7 Level-Sensitive Exit Mode Note 1: After a warm-up period starts, the STOP mode is not reentered if the STOP pin input becomes low or STOP5 to STOP2 becomes high again. Note 2: To return to the level-sensitive exit mode after setting up the edge-sensitive exit mode, the exit mode is not switched until the rising edge of the STOP pin input is detected. (2) Edge-sensitive exit mode (RELM = 0) In this mode, the STOP mode is exited at the rising edge of the STOP pin input. This mode is used in applications where a relatively short program is run repeatedly at periodic intervals. This periodic signal (i.e., a clock from a low-power consumption oscillator) is input input to the STOP pin. In the edge-sensitive exit mode, the STOP mode is entered even if the STOP pin input is high. Disable the STOP5 to STOP2 pin input with the key-on wake-up control register (STOPCR). Example :Entering the STOP mode from the NORMAL mode DI LD (SYSCR1) , 10010000B : IMF0 : Sets the edge-sensitive exit mode to enter the STOP mode STOP pin VIH XOUT pin NORMAL mode Enter the STOP mode by programming. STOP mode Warm-up NORMAL mode STOP mode Exit the STOP mode by hardware at the rising edge of the STOP pin input. Figure 2-8 Edge-Sensitive Exit Mode Page 24 TMP86FS64FG The STOP mode is exited in the edge-sensitive exit mode by the following sequence. 1. Oscillations start. In the dual-clock mode, both high-frequency and low-frequency oscillators start to return to the NORMAL2 mode, and only the low-frequency oscillator starts to return to the SLOW mode. In the single-clock mode, only the high-frequency oscillator starts. 2. The warm-up period time is inserted to allow sufficient time for the oscillator to stabilize. During warm-up, internal operations remain halted. 4 types of warming-up period time can be selected in SYSCR1 Note 1: When the STOP mode is exited, the prescalar and divider of the timing generator are cleared to 0. Note 2: The STOP mode is exited by setting the RESET pin to low, that immediately performs the normal reset operation. Note 3: To exit the STOP mode with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before exiting the STOP mode. The RESET pin must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit is connected, the RESET pin input voltage increases at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if the input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input). Table 2-5 Warm-up Time (fc = 16.0 MHz, fs = 32.768 kHz) Warm-up time [ms] WUT Return to the NORMAL mode Return to the SLOW mode DV1CK=0 00 01 10 11 12.288 4.096 3.072 1.024 DV1CK=1 24.576 8.192 6.144 2.048 750 250 5.85 1.95 Note 1: Since the warm-up period time is obtained by dividing the basic clock by the divider, any frequency fluctuations will lead to small warm-up period time error. The warm-up period time should be considered as an approximate value. Page 25 2.2 System Clock Controller 2. Operational Descriptions Oscillator Oscillated Stopped Main system clock a+3 Stopped Program counter SET (SYSCR1).7 a+2 Instruction execution n+1 n+2 n+3 n+4 Divider n 0 (a) Entering the STOP mode (activated with SET (SYSCR1).7 instruction located at address a) Figure 2-9 Entering and Exiting the STOP Mode a+3 a+4 a+5 Instruction at a+2 address Instruction at a+3 address 0 1 (b) Exiting the STOP mode 2 3 Page 26 Warm-up STOP pin input Oscillator Stopped Oscillated Main system clock a+6 Program counter Instruction Stopped execution Instruction at a+4 address Divider 0 Count up TMP86FS64FG TMP86FS64FG 2.2.4.2 IDLE1/2 and SLEEP1/2 Modes The IDLE1/2 and SLEEP1/2 modes controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is held during the IDLE1/2 or SLEEP1/2 mode. 1. The CPU and watchdog timer are halted. On-chip peripherals continue operation. 2. The data memory, registers, program status words, port output latches hold the status that activated the IDLE1/2 or SLEEP1/2 mode. 3. The program counter holds the address of the instruction after next to the instruction to activate IDLE1/2 or SLEEP1/2 mode. Entering the IDLE1/2 or SLEEP1/2 mode (Instruction) CPU and WDT halted Reset input No No Yes Reset Interrupt request Yes No (Normal execution) IMF = "1" Yes (Interrupt service routine) Interrupt processing Execution of the instruction immediately following the instruction that activated the IDLE1/2 or SLEEP1/2 mode Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 27 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG * Entering IDLE1/2 or SLEEP1/2 mode After clearing the interrupt master enable flag (IMF) to 0, set the individual interrupt enable flag used to exit the IDLE1/2 or SLEEP1/2 mode to 1. To enter the EDLE1/2 or SLEEP1/2 mode, set SYSCR2 Note: When a watchdog timer interrupt is generated immediately before entering the IDEL1/2 or SLEEP1/2 mode, the watchdog timer interrupt is processed without entering the IDEL1/2 or SLEEP1/2 mode. Page 28 Main system clock Interrupt request a+2 a+3 Stopped Program counter SET(SYSCR2).4 Instruction execution Watchdog timer Operated (a) Entering the IDLE1/2 or SLEEP1/2 mode (activated with SET(SYSCR1).4 instruction located at address a) Main system clock Interrupt request a+3 a+4 Figure 2-11 Entering and Exiting the IDLE1/2 or SLEEP1/2 Mode Instruction at a+2 address Operated a+3 Interrupt accepted Operated Page 29 Program counter Instruction execution Stopped Watchdog timer Stopped 1. Normal execution Main system clock Interrupt request Program counter Instruction execution Stopped TMP86FS64FG Watchdog timer Stopped 2. Interrupt service routine (b) Exiting the IDLE1/2 or SLEEP1/2 mode 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG 2.2.4.3 IDLE0 and SLEEP0 Modes The IDLE0 mode is controlled by the system control register 2 (SYSCR2) and time base timer. The following status is held during the IDLE0 mode. * The timing generator stops the clock distribution to the on-chip peripherals except the time base timer. * The data memory, registers, program status words and port output latches hold the status that activated the IDLE0 or SLEEP0 mode. * The program counter holds the address of the instruction after next to the instruction to activate the IDLE0 or SLEEP0 mode. Note: Before entering the IDLE0 or SLEEP0 mode, the on-chip peripherals must be disabled. Stopping operations of the on-chip functions (Instruction) Entering the IDLE0 or SLEEP0 mode (Instruction) CPU and WDT halted Reset input No No Yes Reset Falling the TBT source clock Yes "0" TBTCR Interrupt processing Execution of the instruction immediately following the instruction that activated the IDLE0 or SLEEP0 mode Figure 2-12 IDLE0 or SLEEP0 Mode Page 30 TMP86FS64FG * Entering IDLE0 or SLEEP0 mode Disable on-chip peripherals such as a timer counter. To enter the IDLE0 or SLEEP0 mode, set SYSCR2 Note: The IDLE0 or SLEEP0 mode is entered and exited regardless of TBTCR (1) Program execution resuming with the instruction (IMF, EF8, TBTCR (2) Program execution resuming with the interrupt service routine (IMF, EF8, TBTCR Note 1: The IDLE0 or SLEEP0 mode is returned to the NORMAL1 or SLEEP1 mode by the asynchronous internal clock specified in TBTCR Page 31 Main system clock 2.2 System Clock Controller 2. Operational Descriptions Interrupt request Program counter a+2 a+3 Stopped Instruction execution SET(SYSCR2).2 Watchdog timer Operated (a) Entering the IDLE0 or SLEEP0 mode (activated with SET(SYSCR2).4 instruction located at address a) Main system clock TBT souce clock Figure 2-13 Entering and Exiting the IDLE0 or SLEEP0 Mode a+3 a+4 Instruction at a+2 address Operated a+3 Interrupt accepted Operated Page 32 Program counter Instruction execution Stopped Watchdog timer Stopped 1. Normal execution Main system clock TBT souce clock Program counter Instruction execution Stopped Watchdog timer Stopped TMP86FS64FG 2. Interrupt service routine (b) Exiting the IDLE0 or SLEEP0 mode TMP86FS64FG 2.2.4.4 SLOW Mode The SLOW mode is controlled by the system control register 2 (SYSCR2). (1) Switching the NORMAL2 mode to SLOW mode Write 1 to SYSCR2 Note: The high-frequency clock oscillation can be continued to return quickly to the NORMAL2 mode. To enter the STOP mode from the SLOW mode, the high-frequency clock must be stopped. When the low-frequency clock oscillation is unstable, wait until the oscillation is stabilized before performing the above operation. The TimerCounter (TC2) is convenient to check the low-frequency clock oscillation stability.) Example 1 :Switching from the NORMAL2 mode to SLOW1 mode. SET CLR (SYSCR2) . 5 (SYSCR2) . 7 : SYSCR2 Example 2 :Switching to the SLOW1 mode after checking the low-frequency clock oscillation stability with TC2 SET LD LDW DI SET EI SET | PINTTC2: CLR SET CLR RETI | VINTTC2: DW PINTTC2 : INTTC2 vector table (TC2CR). 5 (SYSCR2). 5 (SYSCR2). 7 : stops INTTC2. : SYSCR2 Page 33 2. Operational Descriptions 2.2 System Clock Controller TMP86FS64FG (2) Switching from the SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to 0, instructions are executed continuously by the low-frequency clock during synchronization period for high-frequency and low-frequency clocks. High-frequency clock fc Low-frequency clock fc Main system clock SYSCK Example :Switching from SLOW1 mode to NORMAL2 mode with TC2 (fc = 16 MHz, warm-up time = 4.0 ms) SET LD LD DI SET EI SET | PINTTC2 CLR CLR RETI | VINTTC2: DW PINTTC2 : INTTC2 vector table (TC2CR). 5 (SYSCR2). 5 : stops TC2. : SYSCR2 Page 34 Highfrequency clock Oscillation stopped Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2).5 SLOW2 mode (a) Switching to the SLOW1 mode CLR (SYSCR2).7 SLOW mode NORMAL2 mode Figure 2-14 Switching between SLOW and NORMAL2 Modes CLR (SYSCR2).5 Warm-up in SLOW2 mode (b) Switching to the NORMAL2 mode Page 35 Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2).7 SLOW1 mode NORMAL2 mode TMP86FS64FG 2. Operational Descriptions 2.3 Reset Circuit TMP86FS64FG 2.3 Reset Circuit TMP86FS64FG has four types of reset, that are an external reset, address trap reset, watchdog timer reset and system clock reset. An address trap reset, watchdog timer reset and system clock reset are internal factor resets. When detecting these reset requests, TMP86FS64FG is in the reset state during a maximum of 24/fc [s]. (During a flash reset, the RESET pin is held high.) Since the internal factor reset circuits that are watchdog timer reset, address trap reset and system clock reset are not initialized upon power-up, a maximum reset time may become 24/fc [s] (1.5 s @ 16.0 MHz). Table 2-6 shows the on-chip hardware initialization by reset operation. Table 2-6 On-Chip Hardware Initialization by Reset Operation On-Chip Hardware Program counter (PC) Stack pointer (SP) General-purpose register (W, A, B, C, D, E, H, L, IX, IY) Jump status flag (JF) Zero flag (ZF) Carry flag (CF) Half carry flag (HF) Sign flag (SF) Overflow flag (VF) Interrupt master enable flag (IMF) Interrupt individual enable flag (EF) Interrupt latch (IL) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latch of I/O port Not initialized Not initialized 0 0 Control register 0 RAM Refer to description of each register Not initialized Refer to description of each I/O port Watchdog timer Enabled Prescaler and divider of the timing generator 0 On-Chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin is the hysteresis input with pull-up resistance. When the RESET pin is held low for a minimum of 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and stable oscillation, a reset is triggered and internal state is initialized. When the RESET pin input goes high, the reset operation is released , and program execution starts at the vector address stored at addresses FFFE to FFFH. Page 36 TMP86FS64FG VDD RESET Reset input Watchdog timer Internal factor reset output circuit Address trap detection System clock detection Figure 2-15 Reset Circuit 2.3.2 Address-Trap-Reset If the CPU runs away due to spurious noises and attempts to fetch an instruction form the on-chip RAM (WDTCR1 Note:Either a reset or an interrupt can be selected for an address-trap. An address-trap area can be specified. Instruction execution Internal reset signal JP a An address-trap is generated Reset released Instruction at r address max 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: "a" is the address in on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog Timer Reset Refer to "Watchdog Timer". 2.3.4 System Clock Reset Either one of the following conditions is met, a system clock reset is generated automatically to prevent the CPU to be in the deadlock condition. (Oscillation is continued.) * SYSCR2 Page 37 2. Operational Descriptions 2.3 Reset Circuit TMP86FS64FG Page 38 TMP86FS64FG 3. Interrupt Control Circuit The TMP86FS64FG has a total of 21 interrupt sources excluding reset, of which 5 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE Interrupt Factors Internal/External Internal Internal Internal Internal External External Internal Internal Internal External Internal External Internal Internal Internal Internal External Internal External Internal Internal (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1, IL8ER = 0 IMF* EF8 = 1, IL8ER = 1 IMF* EF9 = 1, IL9ER = 0 IMF* EF9 = 1, IL9ER = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1, IL13ER = 0 IMF* EF13 = 1, IL13ER = 1 IMF* EF14 = 1, IL14ER = 0 IMF* EF14 = 1, IL14ER = 1 IMF* EF15 = 1, IL15ER = 0 IMF* EF15 = 1, IL15ER = 1 Priority 1 2 2 2 2 5 6 7 8 9 INT1 INTTC4 INTTC5 INTTBT INT2 INTTC1 INT3 INTTC3 INTTC6 INTTC2 INTSIO1 INT4 INTTRX INT5 IL9 FFEC 10 IL10 IL11 IL12 IL13 FFEA FFE8 FFE6 FFE4 11 12 13 14 IL14 FFE2 15 INTADC INTSIO2 IL15 FFE0 16 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. Page 39 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FS64FG The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". Page 40 TMP86FS64FG 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 41 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FS64FG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 42 TMP86FS64FG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTTBT and INT2 share the interrupt source level whose priority is 9. 2. INTTC1 and INT3 share the interrupt source level whose priority is 10. 3. INTSIO1 and INT4 share the interrupt source level whose priority is 14. 4. INTTRX and INT5 share the interrupt source level whose priority is 15. 5. INTADC and INTSIO2 share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH) 7 IL8ER 6 IL9ER 5 4 3 2 IL13ER 1 IL14ER 0 IL15ER (Initial value: 00** *000) IL8ER IL9ER IL13ER IL14ER IL15ER Selects INTTBT or INT2 Selects INTTC1 or INT3 Selects INTSIO1 or INT4 Selects INTTRX or INT5 Selects INTADC or INTSIO2 0: INTTBT 1: INT2 0: INTTC1 1: INT3 0: INTSIO1 1: INT4 0: INTTRX 1: INT5 0: INTADC 1: INTSIO2 R/W R/W R/W R/W R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 43 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86FS64FG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFEEH FFEFH 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. Page 44 TMP86FS64FG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Page 45 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86FS64FG Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Page 46 TMP86FS64FG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86FS64FG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P10 pin function selection are performed by the external interrupt control register (EINTCR). Page 47 3. Interrupt Control Circuit 3.8 External Interrupts TMP86FS64FG Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals.(at CGCR INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT2 INT2 IMF EF8 = 1 and IL8ER=1 Falling edge or Rising edge INT3 INT3 IMF and EF9 = 1 IL9ER=1 Falling edge or Rising edge INT4 INT4 IMF EF13 = 1 and IL13ER=1 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF14 = 1 and IL14ER=1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 48 TMP86FS64FG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC INT0EN Noise reject time select P10/INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port 1: INT0 pin (Port P10 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W INT4 ES INT4 edge select R/W INT3 ES INT2 ES INT1 ES INT3 edge select INT2 edge select INT1 edge select R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 49 3. Interrupt Control Circuit 3.8 External Interrupts TMP86FS64FG Page 50 TMP86FS64FG 4. Special Function Register (SFR) The TMP86FS64FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86FS64FG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H UARTSR RDBUF Reserved Reserved TC1DRAL TC1DRAH TC1DRBL TC1DRBH TC2DRL TC2DRH TC3DRB TC3CR TC2CR TC4CR TC5CR TC6CR TC6DR TC4DR TC5DR IRDACR UARTCR1 UARTCR2 TDBUF P4PRD P3CR P4CR P5CR ADCCR1 ADCCR2 TC3DRA Read P0DR P1DR P2DR P3DR P4DR P5DR P6DR P7DR P0CR P1CR Write Page 51 4. Special Function Register (SFR) 4.1 SFR TMP86FS64FG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read ADCDR2 ADCDR1 SIO1SR SCISEL Reserved P2PRD P4OED P6CR P7CR CGCR TC1CR Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write SIO1CR1 SIO1CR2 - STOPCR WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 52 TMP86FS64FG 4.2 DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH Read Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIO1BR0 SIO1BR1 SIO1BR2 SIO1BR3 SIO1BR4 SIO1BR5 SIO1BR6 SIO1BR7 SIO2BR0 SIO2BR1 SIO2BR2 SIO2BR3 SIO2BR4 SIO2BR5 SIO2BR6 SIO2BR7 Write Page 53 4. Special Function Register (SFR) 4.2 DBR TMP86FS64FG Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H 0FA7H 0FA8H 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H 0FB7H 0FB8H 0FB9H 0FBAH 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH Read Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved P8DR P9DR P8CR P9CR SIO2SR PADR PBDR PACR PBCR PAPU PBPU P6PU P7PU Reserved Reserved Write SIO2CR1 SIO2CR2 Address 0FC0H :: 0FDFH Read Reserved :: Reserved Write Page 54 TMP86FS64FG Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H 0FF6H 0FF7H 0FF8H 0FF9H 0FFAH 0FFBH 0FFCH 0FFDH 0FFEH 0FFFH Read Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SPCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLSCR Write Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 55 4. Special Function Register (SFR) 4.2 DBR TMP86FS64FG Page 56 TMP86FS64FG 5. I/O Ports The TMP86FS64FG have 12 parallel input/output ports (91 pins) as follows. 1. Port P0 (8-bit I/O port) 2. Port P1 (8-bit I/O port) * External interrupt input, timer/counter input, divider output. 3. Port P2 (3-bit I/O port) * External interrupt input, STOP mode release signal input. 4. Port P3 (8-bit I/O port) * Timer/counter input, serial interface input/output. 5. Port P4 (8-bit I/O port) * Timer/counter input, serial interface input/output, external interrupt input. 6. Port P5 (8-bit I/O port) 7. Port P6 (8-bit I/O port) * Analog input. 8. Port P7 (8-bit I/O port) * Analog input, STOP mode release signal input. 9. Port P8 (8-bit I/O port) 10. Port P9 (8-bit I/O port) 11. Port PA (8-bit I/O port) 12. Port PB (8-bit I/O port) Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle Instruction execution cycle Input strobe Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD A, (x) Data input (a) Input timing Fetch cycle Instruction execution cycle Output strobe Fetch cycle Write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD (x), A Data output (b) Output timing Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 57 5. I/O Ports TMP86FS64FG 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P0 input/output control register (P0CR). During reset, the P0CR is initialized to "0", which configures port P0 as an input. The P0 output latches are also initialized to "0". STOP OUTEN P0CRi Data input Data output D Q P0i Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-2 Port P0 P0DR (0000H) 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 (Initial value: 0000 0000) P0CR (0008H) 7 P0CR7 6 P0CR6 5 P0CR5 4 P0CR4 3 P0CR3 2 P0CR2 1 P0CR1 0 P0CR0 (Initial value: 0000 0000) P0CR I/O control for port P0 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 58 TMP86FS64FG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). During reset, the P1CR is initialized to "0", which configures port P1 as an input mode. The P1 output latches are also initialized to "0". It is also used as INT0, INT1, INT2/TC1, TC2, DVO and PPG. When used as secondary function pin, the input pins (INT0, INT1, INT2, TC1,TC2) should be set to the input mode and the output pins (DVO, PPG) should be set to the output mode beforehand the output latch should be set to "1". STOP OUTEN P1CRi Data input Data output D Q P1i Output latch Control output Control input Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-3 Port P1 7 P1DR (0001H) P17 6 P16 5 P15 TC2 4 P14 PPG 3 P13 DVO 2 P12 INT2 TC1 1 P11 INT1 0 P10 INT0 (Initial value: 0000 0000) P1CR (0009H) 7 P1CR7 6 P1CR6 5 P1CR5 4 P1CR4 3 P1CR3 2 P1CR2 1 P1CR1 0 P1CR0 (Initial value: 0000 0000) P1CR I/O control for port P1 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 59 5. I/O Ports TMP86FS64FG 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. During reset, the P2DR is initialized to "1". It is also used as INT5/STOP1. When used as secondary function pin or an input pin, the output latch should be set to "1". In the dual-clock mode, the low-frequency oscillator (32.768 kHz) is connected to P21 (XTIN) and P22 (XTOUT) pins. P2 port output latch (P2DR) and P2 port terminal input (P2R) are located on their respective address. When a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Data input (P20IN) Data input (P20) P20 Data output D Q Output latch Control input Data input (P21IN) Osc.enable Data input (P21) P21 Data output D Q Output latch Data input (P22IN) Data input (P22) P22 Data output D Q Output latch STOP OUTEN XTEN fs Note: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1, XTEN: bit 6 in SYSCR2 Figure 5-4 Port P2 7 P2DR (0002H) 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 0 P20 INT5 STOP1 (Initial value: **** *111) P2R (002CH) Read only 7 6 5 4 3 2 P22IN 1 P21IN 0 P20IN (Initial value: **** ****) Note 1: Port P20 is used as STOP1 pin. Therefore, when stop mode is started, however SYSCR1 Page 60 TMP86FS64FG 5.4 Port P3 (P37 to P30) Port P3 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P3 input/output control register (P3CR). During reset, the P3CR is initialized to "0", which configures port P3 as an input mode. The P3 output latches (P3DR) are also initialized to "1". Port P30, P31 and P32 are also used as TC4/PWM4/PDO4, TC5/PWM5/PDO5 and TC6/PWM6/PDO6. When used as secondary function pin, the input pins (TC4, TC5, TC6) should be set to the input mode and the output pins (PWM4/ PDO4, PWM5/PDO5, PWM6/PDO6) should be set to the output. Port P33, P34, P35, P36 and P37 are also used as SCK1, SI1, SO1, SI2 and SO2. When used as secondary function pin, SCK1 should be set to the input or output mode, SI1 and SI2 should be set to the input mode, SO1 and SO2 should be set to the output mode. STOP OUTEN P3CRi Data input Data output D Q P3i Output latch Control output Control input Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-5 Port P3 7 P3DR (0003H) P37 SO2 6 P36 SI2 5 P35 SO1 4 P34 SI1 3 P33 SCK1 2 P32 TC6 PWM6 PDO6 1 P31 TC5 PWM5 PDO5 0 P30 TC4 PWM4 PDO4 (Initial value: 1111 1111) P3CR (000BH) 7 P3CR7 6 P3CR6 5 P3CR5 4 P3CR4 3 P3CR3 2 P3CR2 1 P3CR1 0 P3CR0 (Initial value: 0000 0000) P3CR I/O control for port P3 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 61 5. I/O Ports TMP86FS64FG 5.5 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P4 input/output control register (P4CR). During reset, the P4CR is initialized to "0", which configures port P4 as an input mode. The P4 output latches are also initialized to "1". It is also used as INT0, INT1, INT2/TC1, TC2, DVO and PPG. When used as secondary function pin, the input pins (INT0, INT1, INT2, TC1, TC2) should be set to the input mode and the output pins (DVO, PPG) should be set to the output mode beforehand the output latch should be set to "1". Port P4 can be configured individually as a tri-state output or sink open drain output under software control. It is specified by the corresponding bit in the P4ODE. During reset, the P4ODE is initialized to "0", and then P4CR is set to "1", the tri-state output is configured. P4 port output latch (P4DR) and P4 port terminal input (P4R) are located on their respective address. When the input mode and output mode are configured simultaneously, even if the bit manipulate instruction is executed, the data of the output latch of the terminal set as the input mode is not influenced of the terminal input. Port P40, P41, P42, P44, P45, P46 and P47 are also used as SCK2, RXD1, TXD1, RXD2, TXD2, INT3/TC3 and INT4. When used as secondary function pin, the SCK1 pin should be set to the input or output mode, the input pins (RXD1, RXD2, INT3/TC3, INT4) should be set to the input mode and the output pins (TXD1, TXD2) should be set to the output. P4ODEi STOP OUTEN P4CRi Data input (P4R) Data input (P4DR) Data output D Q P4i Output latch Control output Control input Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-6 Port P4 Page 62 TMP86FS64FG 7 P4DR (0004H) P47 INT4 6 P46 INT3 TC3 5 P45 TXD2 4 P44 RXD2 3 P43 2 P42 TXD1 1 P41 RXD1 0 P40 SCK2 (Initial value: 1111 1111) P4R (000AH) Read only 7 P47IN 6 P46IN 5 P45IN 4 P44IN 3 P43IN 2 P42IN 1 P41IN 0 P40IN (Initial value: **** ****) P4CR (000CH) 7 P4CR7 6 P4CR6 5 P4CR5 4 P4CR4 3 P4CR3 2 P4CR2 1 P4CR1 0 P4CR0 (Initial value: 0000 0000) P4CR I/O control for port P4 (specified for each bit) 0: Input mode 1: Output mode R/W P4ODE (002DH) 7 P4ODE7 6 P4ODE6 5 P4ODE5 4 P4ODE4 3 P4ODE3 2 P4ODE2 1 P4ODE1 0 P4ODE0 (Initial value: 0000 0000) P4ODE P4 open drain control register (Specified for each bit) 0: Tri-state output 1: Sink open drain output R/W Note: Regardless of P4ODE setting, each terminal has a protect diode. Please refer to section "Input/Output Circuitry; (2) Input/ Output ports". Page 63 5. I/O Ports TMP86FS64FG 5.6 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P5 input/output control register (P5CR). During reset, the P5CR is initialized to "0", which configures port P5 as an input mode. The P5 output latches are also initialized to "0". STOP OUTEN P5CRi Data input Data output D Q P5i Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-7 Port P5 P5DR (0005H) 7 P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 (Initial value: 0000 0000) P5CR (000DH) 7 P5CR7 6 P5CR6 5 P5CR5 4 P5CR4 3 P5CR3 2 P5CR2 1 P5CR1 0 P5CR0 (Initial value: 0000 0000) P5CR I/O control for port P5 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 64 TMP86FS64FG 5.7 Port P6 (P67to P60) Port P6 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Port P6 is also used as an analog input. Input/output mode is specified by the corresponding bit in the port P6 input/output control register (P6CR), P6 output latch (P6DR) and ADCCR1 VDD P6PUi Pull-up resistor (Typ. 80 k) Analog input AINDS SAIN STOP OUTEN P6CRi Data input Data output D Q P6i Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Note 3: SAIN: AD input channel select signal Figure 5-8 Port P6 Page 65 5. I/O Ports TMP86FS64FG P6DR (0006H) 7 P67 AIN7 6 P66 AIN6 5 P65 AIN5 4 P64 AIN4 3 P63 AIN3 2 P62 AIN2 1 P61 AIN1 0 P60 AIN0 (Initial value: 0000 0000) P6CR (002EH) 7 P6CR7 6 P6CR6 5 P6CR5 4 P6CR4 3 P6CR3 2 P6CR2 1 P6CR1 0 P6CR0 (Initial value: 0000 0000) AINDS = 1 (AD unused) P6CR I/O control for port P6 (specified for each bit) P6DR = "0" 0 1 Input "0" fixed #1 P6DR = "1" Input mode AINDS = 0 (AD used) P6DR = "0" AD input #2 P6DR = "1" Input mode R/W Output mode #1 #2 Input data to a pin whose input is fixed to "0" is always "0" regardless of the pin state and whether or not a programmable pull-up resistor is added. When a read instruction for port P6 is executed, the bit of analog input mode becomes read data "0". Note 1: Don't set output mode to pin, which is used for an analog input. Note 2: When used for input mode (include analog input mode), read-modify-write instruction such as bit manipulate instructions cannot be used. Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting input mode read data of terminal, the output latch is changed by these instructions. So P6 port cannot input data. P6PU (0FBCH) 7 P6PU7 6 P6PU6 5 P6PU5 4 P6PU4 3 P6PU3 2 P6PU2 1 P6PU1 0 P6PU0 (Initial value: 0000 0000) P6PU Port P6 pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Note: However the P6PU is set to "1" (pull-up), the port configured output is not set up pull-up resistor. Page 66 TMP86FS64FG 5.8 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Port P7 is also used as an analog input and Key on Wake up input. Input/output mode is specified by the corresponding bit in the port P7 input/output control register (P7CR), P7 output latch (P7DR) and ADCCR1 STOPjEN Key on Wake up P7PUi Analog input AINDS SAIN STOP OUTEN P7CRi Data input Pull-up resistor (Typ. 80 k) VDD Data output D Q P7i Output latch Note 1: i = 7 to 0, j = 5 to 2 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Note 3: SAIN: bit 0 to 3 in ADCCRA Note 4: SOTPjEN: bit 4 to 7 in STOPCR Figure 5-9 Port P7 Page 67 5. I/O Ports TMP86FS64FG 7 P7DR (0007H) P77 AIN15 STOP5 6 P76 AIN14 STOP4 5 P75 AIN13 STOP3 4 P74 AIN12 STOP2 3 P73 AIN11 2 P72 AIN10 1 P71 AIN9 0 P70 AIN8 (Initial value: 0000 0000) P7CR (002FH) 7 P7CR7 6 P7CR6 5 P7CR5 4 P7CR4 3 P7CR3 2 P7CR2 1 P7CR1 0 P7CR0 (Initial value: 0000 0000) AINDS = 1 (AD unused) P7CR I/O control for port P7 (specified for each bit) P7DR = "0" 0 1 Input "0" fixed #1 P7DR = "1" Input mode AINDS = 0 (AD used) P7DR = "0" AD input #2 P7DR = "1" Input mode R/W Output mode #1 #2 Input data to a pin whose input is fixed to "0" is always "0" regardless of the pin state and whether or not a programmable pull-up resistor is added. When a read instruction for port P7 is executed, the bit of analog input mode becomes read data "0". Note 1: Don't set output mode to pin, which is used for an analog input. Note 2: When used for input mode (include analog input mode), read-modify-write instruction such as bit manipulate instructions cannot be used. Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting input mode read data of terminal, the output latch is changed by these instructions. So P7 port cannot input data. P7PU (0FBDH) 7 P7PU7 6 P7PU6 5 P7PU5 4 P7PU4 3 P7PU3 2 P7PU2 1 P7PU1 0 P7PU0 (Initial value: 0000 0000) P7PU Port P7 pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Note: However the P7PU is set to "1" (pull-up), the port configured output is not set up pull-up resistor. Page 68 TMP86FS64FG 5.9 Port P8 (P87 to P80) Port P8 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P8 input/output control register (P8CR). During reset, the P8CR is initialized to "0", which configures port P8 as an input. The P8 output latches are also initialized to "0". STOP OUTEN P8CRi Data input Data output D Q P8i Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-10 Port P8 P8DR (0FB0H) 7 P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 (Initial value: 0000 0000) P8CR (0FB2H) 7 P8CR7 6 P8CR6 5 P8CR5 4 P8CR4 3 P8CR3 2 P8CR2 1 P8CR1 0 P8CR0 (Initial value: 0000 0000) P8CR I/O control for port P8 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 69 5. I/O Ports TMP86FS64FG 5.10 Port P9 (P97 to P90) Port P9 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P9 input/output control register (P9CR). During reset, the P9CR is initialized to "0", which configures port P9 as an input. The P9 output latches are also initialized to "0". STOP OUTEN P9CRi Data input Data output D Q P9i Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-11 Port P9 P9DR (0FB1H) 7 P97 6 P96 5 P95 4 P94 3 P93 2 P92 1 P91 0 P90 (Initial value: 0000 0000) P9CR (0FB3H) 7 P9CR7 6 P9CR6 5 P9CR5 4 P9CR4 3 P9CR3 2 P9CR2 1 P9CR1 0 P9CR0 (Initial value: 0000 0000) P9CR I/O control for port P9 (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Page 70 TMP86FS64FG 5.11 Port PA (PA7 to PA0) Port PA is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port PA input/output control register (PACR). During reset, the PACR is initialized to "0", which configures port PA as an input. The PA output latches are also initialized to "0". VDD PAPUi STOP OUTEN Pull-up resistor (Typ. 80 k) PACRi Data input Data output D Q PAi Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-12 Port PA PADR (0FB6H) 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 0 PA0 (Initial value: 0000 0000) PACR (0FB8H) 7 PACR7 6 PACR6 5 PACR5 4 PACR4 3 PACR3 2 PACR2 1 PACR1 0 PACR0 (Initial value: 0000 0000) PACR I/O control for port PA (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. PAPU (0FBAH) 7 PAPU7 6 PAPU6 5 PAPU5 4 PAPU4 3 PAPU3 2 PAPU2 1 PAPU1 0 PAPU0 (Initial value: 0000 0000) PAPU Port PA pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Note: However the PAPU is set to "1" (pull-up), the port configured output is not set up pull-up resistor. Page 71 5. I/O Ports TMP86FS64FG 5.12 Port PB (PB7 to PB0) Port PB is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port PB input/output control register (PBCR). During reset, the PBCR is initialized to "0" which configures port PB as an input. The PB output latches are also initialized to "0". VDD PBPUi STOP OUTEN Pull-up resistor (Typ. 80 k) PBCRi Data input Data output D Q PBi Output latch Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-13 Port PB and PBCR PBDR (0FB7H) 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 (Initial value: 0000 0000) PBCR (0FB9H) 7 PBCR7 6 PBCR6 5 PBCR5 4 PBCR4 3 PBCR3 2 PBCR2 1 PBCR1 0 PBCR0 (Initial value: 0000 0000) PBCR I/O control for port PB (specified for each bit) 0: Input mode 1: Output mode R/W Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Readmodify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. PBPU (0FBBH) 7 PBPU7 6 PBPU6 5 PBPU5 4 PBPU4 3 PBPU3 2 PBPU2 1 PBPU1 0 PBPU0 (Initial value: 0000 0000) PBPU Port PB pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Note: However the PBPU is set to "1" (pull-up), the port configured output is not set up pull-up resistor. Page 72 TMP86FS64FG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 Watchdog Timer Configuration Reset release fc/2 ,fc/2 or fs/2 fc/221,fc/222 or fs/213 fc/219,fc/220 or fs/211 fc/217,fc/218 or fs/29 23 24 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 6-1 Watchdog Timer Configuration Page 73 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86FS64FG 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 74 TMP86FS64FG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV1CK=0 DV1CK=1 226/fc 224/fc 222fc 220/fc DV7CK = 1 DV1CK=0 217/fs 215/fs 213/fs 211/fs DV1CK=1 217/fs 215/fs 213/fs 211/fs 217/fs 215fs 213fs 211/fs SLOW1/2 mode Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 6.2.2 Watchdog Timer Enable Setting WDTCR1 Page 75 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86FS64FG 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 DV1CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m DV1CK = 1 4.194 1.049 262.144 m 65.536 m NORMAL1/2 mode DV7CK = 1 DV1CK = 0 4 1 250 m 62.5 m DV1CK = 1 4 1 250 m 62.5 m 4 1 250 m 62.5 m SLOW mode 6.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 083FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 76 TMP86FS64FG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 6-2 Watchdog Timer Interrupt Page 77 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86FS64FG 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 6.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 6.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 6.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 78 TMP86FS64FG 6.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 79 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86FS64FG Page 80 TMP86FS64FG 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX fc/223,fc/224 or fs/215 fc/221,fc/222 or fs/213 fc/216,fc/217 or fs/28 fc/214,fc/215 or fs/26 fc/213,fc/214 or fs/25 fc/212,fc/213 or fs/24 fc/211,fc/212 or fs/23 fc/29,fc/210 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 7-1 Time Base Timer configuration 7.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer Enable / Disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV1CK=0 000 001 fc/223 fc/221 fc/216 fc/214 fc/213 fc/212 fc/2 11 9 DV7CK = 1 DV1CK=0 fs/215 fs/213 fs/28 fs/26 fs/25 fs/24 fs/2 3 DV1CK=1 fc/224 fc/222 fc/217 fc/215 fc/214 fc/213 fc/2 fc/2 12 10 DV1CK=1 fs/215 fs/213 fs/28 fs/26 fs/25 fs/24 fs/2 3 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/2 fs/2 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 81 7. Time Base Timer (TBT) 7.1 Time Base Timer TMP86FS64FG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRH) . 0 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV1CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 DV1CK = 1 0.95 3.81 122.07 488.28 976.56 1953.13 3906.25 15625 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 DV1CK = 0 1 4 128 512 1024 2048 4096 16384 DV1CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 7.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 7-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 7-2 Time Base Timer Interrupt Page 82 TMP86FS64FG 7.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 7.2.1 Configuration Output latch Data output D Q DVO pin fc/213,fc/214 or fs/25 fc/212,fc/213 or fs/24 fc/211,fc/212 or fs/23 fc/210,fc/211 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 7-3 Divider Output 7.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK=0 DV7CK=1 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DV1CK = 0 DV1CK = 1 DV1CK = 0 DV1CK = 1 DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 fc/214 fc/213 fc/212 fc/211 fs/25 fs/24 fs/23 fs/22 fs/25 fs/24 fs/23 fs/22 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 83 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) TMP86FS64FG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV1CK=0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV1CK=1 976.6 1.953 k 3.906 k 7.813 k DV7CK = 1 DV1CK=0 1.024 k 2.048 k 4.096 k 8.192 k DV1CK=1 1.024 k 2.048 k 4.096 k 8.192 k 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode Page 84 MCAP1 S INTTC1 interript A TC1S Y 8.1 Configuration B Start MPPG1 TC1S clear Clear PPG output mode 2 Decoder Set Q Command start Pulse width measurement mode External trigger External trigger start Rising Falling Edge detector METT1 TC1 Clear Y Source clock Match CMP 16-bit up-counter 8. 16-Bit TimerCounter 1 (TC1) Port (Note) D Figure 8-1 TimerCounter 1 (TC1) Pulse width measurement mode S Toggle Q Clear Selector S Q Set Capture TC1DRB TC1DRA 16-bit timer register A, B Toggle Enable Set Clear PPG output mode Internal reset Write to TC1CR TFF1 Page 85 fc/211, fc/212, fs/23 A B fc/27, fc/26 B Y A fc/23, fc/24 C S 2 Window mode Port (Note) pin ACAP1 TC1CK TC1CR TC1 control register TMP86FS64FG Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". 8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control TMP86FS64FG 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 TC1DRA (0021H, 0020H) TC1DRB (0023H, 0022H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC1DRAH (0021H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0023H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0020H) Read/Write TC1DRBL (0022H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 1 Control Register 7 TC1CR (0032H) 6 ACAP1 MCAP1 METT1 MPPG1 5 4 3 2 1 0 Read/Write (Initial value: 0000 0000) TFF1 TC1S TC1CK TC1M TFF1 ACAP1 MCAP1 METT1 MPPG1 Timer F/F1 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC1S TC1 start control - O O O O O R/W - O O O O O NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 TC1CK TC1 source clock select [Hz] 00 01 10 11 TC1 operating mode select fc/2 11 DV7CK = 1 DV1CK = 0 fs/2 3 Divider DV1CK = 1 fc/2 12 DV1CK = 1 fs/23 fc/28 fc/2 4 SLOW, SLEEP mode fs/23 - - R/W DV9 DV5 DV1 fc/27 fc/2 3 fc/28 fc/2 4 fc/27 fc/2 3 External clock (TC1 pin input) TC1M 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register. Page 86 TMP86FS64FG Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR1 during TC1S=00. Set the timer F/F1 control until the first timer start after setting the PPG mode. Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to "0" in the mode except PPG output mode. Note 7: Set TC1DRB after setting TC1M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC1S) is cleared to "00" automatically, and the timer stops. After the STOP mode is exited, set the TC1S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 87 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR NORMAL1/2, IDLE1/2 mode TC1CK DV7CK = 0 DV1CK = 0 Resolution [s] 00 01 10 128 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m DV1CK = 1 Resolution [s] 256 16 1 Maximum Time Setting [s] 16.78 1.05 65.53 m DV1CK = 0 Resolution [s] 244.14 8.0 0.5 Maximum Time Setting [s] 16.0 0.524 32.77 m DV7CK = 1 DV1CK = 1 Resolution [s] 244.14 16.0 1.0 Maximum Time Setting [s] 16.0 0.838 52.42 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - SLOW, SLEEP mode Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC1CR), 00000000B (TC1CR), 00010000B (EIRH). 1 (TC1DRA), 1E84H ; Sets the timer register (1 s / 211/fc = 1E84H) ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 Example 2 :Auto-capture LD : LD (TC1CR), 01010000B : WA, (TC1DRB) ; Reads the capture value ; ACAP1 1 Note: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 88 TMP86FS64FG Timer start Source clock Counter TC1DRA 0 ? 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 n INTTC1 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture TC1DRB ? m-1 m m+1 m+2 n-1 Capture n n+1 ACAP1 (b) Auto-capture Figure 8-2 Timer Mode Timing Chart Page 89 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin (fc =16 MHz, CGCR LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 00100100B (EIRH). 1 (TC1DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin (fc =16 MHz, CGCR LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 01110100B (EIRH). 1 (TC1DRA), 01F4H ; 4 ms / 27/fc = 1F4H ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Page 90 TMP86FS64FG Count start TC1 pin input Count start At the rising edge (TC1S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC1DRA n Match detect Count clear INTTC1 interrupt request (a) Trigger start (METT1 = 0) At the rising edge (TC1S = 10) Count start TC1 pin input Count clear Count start Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC1DRA n Match detect Count clear INTTC1 interrupt request Note: m < n (b) Trigger start and stop (METT1 = 1) Figure 8-3 External Trigger Timer Mode Timing Chart Page 91 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR Timer start TC1 pin Input Up-counter TC1DRA INTTC1 interrput request ? 0 1 2 n-1 n 0 1 2 At the rising edge (TC1S = 10) n Match detect Counter clear Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulse Width to TC1 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode High-going Low-going 23/fc 23/fc SLOW1/2, SLEEP1/2 Mode 23/fs 23/fs Page 92 TMP86FS64FG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC1CR Count start Timer start Count stop Count start TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request ? 7 Match detect (a) Positive logic (TC1S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request (b) Negative logic (TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-5 Window Mode Timing Chart Page 93 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR Note 1: The captured value must be read from TC1DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC1DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 94 TMP86FS64FG Example :Duty measurement (resolution fc/27 [Hz], CGCR CLR LD DI SET EI LD : PINTTC1: CPL JRS LD LD LD RETI SINTTC1: LD LD LD : RETI : VINTTC1: DW PINTTC1 ; INTTC1 Interrupt vector ; Duty calculation A, (TC1DRBL) W,(TC1DRBH) (WIDTH), WA ; Stores cycle in RAM ; Reads TC1DRB (Cycle) (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W,(TC1DRBH) (HPULSE), WA ; Stores high-level pulse width in RAM ; Reads TC1DRB (High-level pulse width) ; INTTC1 interrupt, inverts and tests INTTC1 service switch (TC1CR), 00100110B (EIRH). 1 (INTTC1SW). 0 (TC1CR), 00000110B ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 ; Sets the TC1 mode and source clock ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Starts TC1 with an external trigger at MCAP1 = 0 WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW Page 95 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG Count start TC1 pin input Trigger Count start (TC1S = "10") Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start Count start (TC1S = "10") TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP1 = "0") 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 Figure 8-6 Pulse Width Measurement Mode Page 96 TMP86FS64FG 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC1CR Since the output level of the PPG pin can be set with TC1CR Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC1CR Page 97 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 MHz, CGCR Setting port LD LDW LDW LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc ms = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz, CGCR Setting port LD LDW LDW LD : LD LD LD LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B : (TC1CR), 10000111B (TC1CR), 10000100B (TC1CR), 00000111B (TC1CR), 00010111B ; Stops the timer ; Sets the timer mode ; Sets the PPG mode, TFF1 = 0 ; Starts the timer ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc s = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer I/O port output latch shared with PPG output Data output D R Q Port output enable PPG pin Function output TC1CR Figure 8-7 PPG Output Page 98 TMP86FS64FG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Note: m > n (a) Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC1DRB n TC1DRA m PPG pin output INTTC1 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC1S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 99 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS64FG Page 100 TMP86FS64FG 9. 16-Bit Timer/Counter2 (TC2) 9.1 Configuration TC2S H Window TC2 pin 23 Port (Note) 24, 15 fc/2 , fc/2 fs/2 fc/213, fc/214, fs/25 fc/28, fc/29 fc/23, fc/24 fc fs A B C D E F S 3 TC2CK B Timer/ event counter Clear Y A S Source clock 16-bit up counter TC2M TC2S TC2CR TC2DR 16-bit timer register 2 CMP Match INTTC2 interrupt TC2 control register Note: When control input/output is used, I/O port setting should be set correctly. For details, refer to the section "I/O ports". Figure 9-1 Timer/Counter2 (TC2) Page 101 9. 16-Bit Timer/Counter2 (TC2) 9.2 Control TMP86FS64FG 9.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2DR (0025H, 0024H) TC2DRH (0025H) (Initial value: 1111 1111 1111 1111) TC2DRL (0024H) R/W TC2CR (0013H) 7 6 5 TC2S 4 3 TC2CK 2 1 0 TC2M (Initial value: **00 00*0) TC2S TC2 start control 0:Stop and counter clear 1:Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 000 001 fc/2 23 R/W DV7CK = 1 DV1CK = 0 fs/2 15 Divider SLOW1/2 mode fs/215 fs/25 - - fc (Note7) - SLEEP1/2 mode fs/215 fs/25 - - - - R/W DV1CK = 1 fc/2 24 DV1CK = 1 fs/215 fs/25 fc/29 fc/24 - fs DV21 DV11 DV6 DV1 - - fc/213 fc/28 fc/23 - fs fc/214 fc/29 fc/24 - fs fs/25 fc/28 fc/23 - fs TC2CK TC2 source clock select Unit : [Hz] 010 011 100 101 110 111 Reserved External clock (TC2 pin input) R/W TC2M TC2 operating mode select 0:Timer/event counter mode 1:Window mode Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect. Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper side (TC2DRH) after writing data to the lower side (TC2DRL). Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0). Note 5: Values to be loaded to the timer register must satisfy the following condition. TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up) Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable. Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected. Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC2S again. Page 102 TMP86FS64FG 9.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a interrupt by matching upper 5-bits only. Though, in this situation, it is necessary to set TC2DRH only. Table 9-1 Source Clock (Internal clock) for Timer/Counter2 (at fc = 16 MHz, DV7CK=0) TC2C K DV1CK = 0 Maximum Time Setting 9.54 [h] 33.55 [s] 1.05 [s] 32.77 [ms] - 2 [s] NORMAL1/2, IDLE1/2 mode SLOW1/2 mode DV7CK = 0 DV1CK = 1 Maximum Time Setting 19.1 [h] 1.12 [min] 2.09 [s] 65.5 [ms] - 2 [s] DV1CK = 0 Maximum Time Setting 18.2 [h] 1.07 [min] 1.05 [s] 32.77 [ms] - 2 [s] DV7CK = 1 DV1CK = 1 Maximum Time Setting 18.2 [h] 1.07 [min] 2.10 [s] 65.5 [ms] - 2 [s] Maximum Time Setting 18.2 [h] 1.07 [min] - - - - Maximum Time Setting 18.2 [h] 1.07 [min] - - - - SLEEP1/2 mode Resolution Resolution Resolution Resolution Resolution Resolution 000 001 010 011 100 101 524.29 [ms] 512.0 [s] 16.0 [s] 0.5 [s] - 30.52 [s] 1.05 [s] 1.02 [ms] 32 [s] 1.0 [s] - 30.52 [s] 1 [s] 0.98 [ms] 16.0 [s] 0.5 [s] - 30.52 [s] 1 [s] 0.98 [ms] 32.0 [s] 1.0 [s] - 30.52 [s] 1 [s] 0.98 [ms] - - 62.5 [ns] - 1 [s] 0.98 [ms] - - - - Note:When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW1 mode to NORMAL2 mode. Example :Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz, CGCR LDW DI SET EI LD LD (TC2CR), 00001000B (TC2CR), 00101000B (EIRH). 4 (TC2DR), 061AH ; Sets TC2DR (25 ms 28/fc = 061AH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; Source clock / mode select ; Starts Timer Page 103 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86FS64FG Timer start Source clock Up-counter 0 1 2 3 4 Match detect n0 1 2 3 Counter clear TC2DR INTTC2 interrupt Figure 9-2 Timer Mode Timing Chart Page 104 TMP86FS64FG 9.3.2 Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is cleared. Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at the falling edge after the match of TC2DR and up counter. The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW DI SET EI LD LD (TC2CR), 00011100B (TC2CR), 00111100B (EIRH). 4 (TC2DR), 640 ; Sets TC2DR ; IMF= "0" ;Enables INTTC2 interrupt ; IMF= "1" ; TC2 source vclock / mode select ; Starts TC2 Table 9-2 Timer/Counter 2 External Input Clock Pulse Width Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 mode "H" width "L" width 23/fc 23/fc SLOW1/2, SLEEP1/2 mode 23/fs 23/fs Timer start TC2 pin input Counter 0 1 2 3 Match detect n 0 1 2 3 Counter clear TC2DR n INTTC2 interrupt Figure 9-3 Event Counter Mode Timing Chart 9.3.3 Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (Window pulse) is "H" level. The contents of TC2DR are compared with the contents of up counter. If a match found, an INTTC2 interrupt is generated, and the up-counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock by the TC2CR Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL mode, the timer should be halted by setting TC2CR Page 105 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86FS64FG Example :Generates an interrupt, inputting "H" level pulse width of 120 ms or more. (at fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC2CR), 00000101B (TC2CR), 00100101B (EIRH). 4 (TC2DR), 00EAH ; Sets TC2DR (120 ms 213/fc = 00EAH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; TC2sorce clock / mode select ; Starts TC2 Timer start TC2 pin input Internal clock Counter TC2DR Match detect INTTC2 interrupt Counter clear 1 2 n 0 1 2 3 Figure 9-4 Window Mode Timing Chart Page 106 TMP86FS64FG 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration Falling Edge detector Rising TC3 pin TC3S INTTC3 interrupt Clear Port (Note) fc/213, fs/2 5 fc/212, fs/2 4 fc/211 , fs/2 3 fc/210, fs/2 2 fc/29 , fs/2 fc/28 fc/27 H AY B C D E F G S 3 Source clock 8-bit up-counter Overflow detect TC3S CMP Match detect A B S Y TC3DRB Capture TC3DRA Capture 8-bit timer register TC3CK TC3M TC3CR TC3 contorol register Note: Function input may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 10-1 TimerCounter 3 (TC3) ACAP TC3S Page 107 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86FS64FG 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB). Timer Register and Control Register TC3DRA (0010H) TC3DRB (0011H) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) Read only (Initial value: 1111 1111) TC3CR (0012H) 7 6 ACAP 5 4 TC3S 3 2 TC3CK 1 0 TC3M (Initial value: *0*0 0000) ACAP TC3S Auto capture control TC3 start control 0: - 1: Auto capture 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK=0 000 001 fc/213 fc/212 fc/211 fc/2 10 R/W R/W SLOW1/2, SLEEP1/2 mode fs/25 fs/24 fs/23 fs/2 2 DV7CK = 1 DV1CK=0 fs/25 fs/24 fs/23 fs/2 2 Divider DV1CK=1 fc/214 fc/213 fc/212 fc/2 11 DV1CK=1 fs/25 fs/24 fs/23 fs/2 2 DV11 DV10 DV9 DV8 DV7 DV6 DV5 TC3CK TC3 source clock select [Hz] 010 011 100 101 110 111 R/W fc/29 fc/2 fc/2 8 7 fc/210 fc/2 fc/2 9 8 fs/2 fc/2 fc/2 8 7 fs/2 fc/2 fc/2 9 8 fs/2 - - External clock (TC3 pin input) R/W TC3M TC3 operating mode select 0: Timer/event counter mode 1: Capture mode Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: Set the operating mode and source clock when TimerCounter stops (TC3S = 0). Note 3: To set the timer registers, the following relationship must be satisfied. TC3DRA > 1 (Timer/event counter mode) Note 4: Auto-capture (ACAP) can be used only in the timer and event counter modes. Note 5: When the read instruction is executed to TC3CR, the bit 5 and 7 are read as a don't care. Note 6: Do not program TC3DRA when the timer is running (TC3S = 1). Note 7: When the STOP mode is entered, the start control (TC3S) is cleared to 0 automatically, and the timer stops. After the STOP mode is exited, TC3S must be set again to use the timer counter. Page 108 TMP86FS64FG 10.3 Function TimerCounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 3A (TC3DRA) value is detected, an INTTC3 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC3CR Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Clock TC3DRA Up-counter Match detect C8 C6 C7 C8 00 01 TC3DRB C6 C7 C8 01 Note: In the case that TC3DRB is C8H Figure 10-2 Auto-Capture Function Table 10-1 Source Clock for TimerCounter 3 (Example: fc = 16 MHz, fs = 32.768 kHz) TC3CK DV7CK = 0 DV1CK = 0 Resolution [s] 000 001 010 011 100 101 110 512 256 128 64 32 16 8 Maximum Time Setting [ms] 130.6 65.3 32.6 16.3 8.2 4.1 2.0 DV1CK = 1 Resolution [s] 1024 512 256 128 64 32 16 Maximum Time Setting [ms] 261.1 130.6 65.3 32.6 16.3 8.2 4.1 DV1CK = 0 Resolution [s] 976.56 488.28 244.14 122.07 61.01 16.0 8.0 Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15.6 4.1 2.0 NORMAL1/2, IDLE1/2 mode DV7CK = 1 DV1CK = 1 Resolution [s] 976.56 488.28 244.14 122.07 61.01 32.0 16.0 Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15.6 8.2 4.1 Resolution [s] 976.56 488.28 244.14 122.07 61.01 - - Resolution [ms] 249.0 124.5 62.3 31.1 15.6 - - SLOW1/2, SLEEP1/2 mode Page 109 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86FS64FG Timer start Source clock Counter 0 1 2 3 4 n0 1 2 3 4 5 6 7 TC3DRA INTTC3 interrupt ? n Match detect Counter clear (a) Timer mode Source clock Counter m m+1 m+2 n n+1 Capture TC3DRB ? m m+1 m+2 n Capture n+1 TC3CR Figure 10-3 Timer Mode Timing Chart Page 110 TMP86FS64FG 10.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC3 pin. When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and up-counter is cleared. After being cleared, the up-counter restarts counting at each rising edge of the input pulse to the TC3 pin. Since a match is detected at the falling edge of the input pulse to TC3 pin, an INTTC3 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC3DRA. The maximum applied frequencies are shown in Table 10-2. The pulse width larger than one machine cycle is required for high-going and low-going pulses. Setting TC3CR Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s LD LD LD (TC3CR), 00001110B (TC3DRA), 19H (TC3CR), 00011110B : Sets the clock mode : 0.5 s / 1/50 = 25 = 19H : Starts TC3. Table 10-2 Maximum Frequencies Applied to TC3 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 22/fc 22/fc SLOW1/2, SLEEP1/2 mode 22/fs 22/fs Timer start TC3 pin input Counter 0 1 2 3 n Match detect 0 1 2 3 Counter clear TC3DRA INTTC3 interrupt n Figure 10-4 Event Counter Mode Timing Chart Page 111 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP86FS64FG 10.3.3 Capture Mode In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are measured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60 Hz. When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is captured into TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and the INTTC3 interrupt request is generated. The up-counter is cleared at this time. Generally, read TC3DRB and TC3DRA during INTTC3 interrupt processing. After the up-counter is cleared, counting is continued and the next up-counter value is captured into TC3DRB. When the rising edge is detected immediately after the timer starts, the up-counter value is captured into TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When the read instruction is executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset) is read. The minimum input pulse width must be larger than one cycle width of the source clock programmed in TC3CR Timer start TC3CR 0 1 i-1 i i+1 k-1 k 0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF 0 1 2 3 Figure 10-5 Capture Mode Timing Chart Page 112 TMP86FS64FG 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TC4S fc/211, fc212 or fs/23 fc/27, fc28 fc/25, fc26 fc/23, fc24 fc/22, fc23 fc/2, fc22 fc, fc/2 (Note) A B Source C Clock Clear D EY Y 8-bit up-counter F G H S 3 CMP Overflow detect 0 1 Match detect S Y TC4 pin Timer F/F TC4CK Toggle Port (Note) TC4S TC4M 2 0 Y 1 Clear S PWM output mode PWM4/ PDO4/ pin TC4CR TC4DR TC4S INTTC4 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 11-1 TimerCounter 4 (TC4) Page 113 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86FS64FG 11.2 TimerCounter Control The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and timer registers 4 (TC4DR). Timer Register and Control Register TC4DR (0018) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC4CR (0014) 7 6 5 TC4S 4 3 TC4CK 2 1 TC4M 0 Read/Write (Initial value: **00 0000) TC4S TC4 start control 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 000 001 fc/211 fc/27 fc/25 fc/2 3 R/W SLOW1/2, SLEEP1/2 mode fs/23 - - - - - - R/W DV7CK = 1 DV1CK = 0 fs/23 fc/27 fc/25 fc/2 3 Divider DV1CK = 1 fc/212 fc/28 fc/26 fc/2 4 DV1CK = 1 fs/23 fc/28 fc/26 fc/2 4 DV9 DV5 DV3 DV1 - - - TC4CK TC4 source clock select [Hz] 010 011 100 101 110 111 fc/22 fc/2 fc fc/23 fc/22 fc/2 fc/22 fc/2 fc fc/23 fc/22 fc/2 External clock (TC4 pin input) TC4M TC4 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: To set the timer registers, the following relationship must be satisfied. 1 TC4DR 255 Note 3: To start timer operation (TC4S = 0 1) or disable timer operation (TC4S = 1 0), do not change the TC4CR Timer Mode 000 001 010 TC4CK 011 100 101 110 111 O O O O - - - - Event Counter Mode - - - - - - - O PDO Mode O O O - - - - - PWM Mode - - - O O O O x Page 114 TMP86FS64FG Note: O : Available source clock Page 115 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86FS64FG 11.3 Function TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 11.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 11-1 Source Clock for TimerCounter 4 (Example: fc = 16 MHz, fs = 32.768 kHz) NORMAL1/2, IDLE1/2 Mode TC4CK DV1CK = 0 Maximum Time Setting [ms] 32.6 2.0 0.510 0.128 DV7CK = 0 DV1CK = 1 Maximum Time Setting [ms] 65.3 4.1 1.0 0.255 DV1CK = 0 Maximum Time Setting [ms] 62.2 2.0 0.510 0.128 DV7CK = 1 DV1CK = 1 Maximum Time Setting [ms] 62.2 4.1 1.0 0.255 Maximum Time Setting [ms] 62.2 - - - SLOW1/2, SLEEP1/2 Mode Resolution [s] Resolution [s] Resolution [s] Resolution [s] Resolution [s] 000 001 010 011 128.0 8.0 2.0 0.5 256.0 16.0 4.0 1.0 244.14 8.0 2.0 0.5 244.14 16.0 4.0 1.0 244.14 - - - Page 116 TMP86FS64FG 11.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4 pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR. The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not supplied in these modes. Table 11-2 External Source Clock for TimerCounter 4 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 23/fc 23/fc Page 117 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86FS64FG 11.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is low, the duty pulse may be shorter than the programmed value. Example :Generating 1024 Hz pulse (fc = 16.0 Mhz) LD LD LD (TC4CR), 00000110B (TC4DR), 3DH (TC4CR), 00100110B : Sets the PDO mode. (TC4M = 10, TC4CK = 001) : 1/1024 / 27/fc / 2 (half cycle period) = 3DH : Start TC4 Internal clock Counter TC4DR Timer F/F 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 n Match detect PDO4 pin INTTC4 interrupt request Figure 11-2 PDO Mode Timing Chart Page 118 TMP86FS64FG 11.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4 pin becomes high. The INTTC4 interrupt request is generated at this time. When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is low, one PMW cycle may be shorter than the programmed value. TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes. Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated (typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is issued. TC4CR Internal clock Counter TC4DR 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite ? n m Rewrite p Rewrite Data shift m Data shift Shift register Timer F/F ? n Data shift Match detect Match detect Match detect PWM4 pin INTTC4 interrupt request n n m PWM cycle Figure 11-3 PWM output Mode Timing Chart (TC4) Page 119 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP86FS64FG Table 11-3 PWM Mode (Example: fc = 16 MHz) NORMAL1/2, IDLE1/2 Mode TC4CK DV1CK = 0 Resolution [ns] 000 001 010 011 100 101 110 - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 0 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - DV1CK = 0 Resolution [ns] - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 1 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - Page 120 TMP86FS64FG 12. 8-Bit TimerCounter 5 (TC5) 12.1 Configuration TC5S fc/211, fc212 or fs/23 fc/27, fc28 fc/25, fc26 fc/23, fc24 fc/22, fc23 fc/2, fc22 fc, fc/2 (Note) A B Source C Clock Clear D EY Y 8-bit up-counter F G H S 3 CMP Overflow detect 0 1 Match detect S Y TC5 pin Timer F/F TC5CK Toggle Port (Note) TC5S TC5M 2 0 Y 1 Clear S PWM output mode PWM5/ PDO5/ pin TC5CR TC5DR TC5S INTTC5 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 12-1 TimerCounter 5 (TC5) Page 121 12. 8-Bit TimerCounter 5 (TC5) 12.1 Configuration TMP86FS64FG 12.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and timer registers 5 (TC5DR). Timer Register and Control Register TC5DR (0019) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC5CR (0015) 7 6 5 TC5S 4 3 TC5CK 2 1 TC5M 0 Read/Write (Initial value: **00 0000) TC5S TC5 start control 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 000 001 fc/211 fc/27 fc/25 fc/2 3 R/W SLOW1/2, SLEEP1/2 mode fs/23 - - - - - - R/W DV7CK = 1 DV1CK = 0 fs/23 fc/27 fc/25 fc/2 3 Divider DV1CK = 1 fc/212 fc/28 fc/26 fc/2 4 DV1CK = 1 fs/23 fc/28 fc/26 fc/2 4 DV9 DV5 DV3 DV1 - - - TC5CK TC5 source clock select [Hz] 010 011 100 101 110 111 fc/22 fc/2 fc fc/23 fc/22 fc/2 fc/22 fc/2 fc fc/23 fc/22 fc/2 External clock (TC5 pin input) TC5M TC5 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: To set the timer registers, the following relationship must be satisfied. 1 TC5DR 255 Note 3: To start timer operation (TC5S = 0 1) or disable timer operation (TC5S = 1 0), do not change the TC5CR Timer Mode 000 001 010 TC5CK 011 100 101 110 111 O O O O - - - - Event Counter Mode - - - - - - - O PDO Mode O O O - - - - - PWM Mode - - - O O O O x Page 122 TMP86FS64FG Note: O : Available source clock Page 123 12. 8-Bit TimerCounter 5 (TC5) 12.1 Configuration TMP86FS64FG 12.3 Function TimerCounter 5 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 12.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC5DR value is detected, an INTTC5 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 12-1 Source Clock for TimerCounter 5 (Example: fc = 16 MHz, fs = 32.768 kHz) NORMAL1/2, IDLE1/2 Mode TC5CK DV1CK = 0 Maximum Time Setting [ms] 32.6 2.0 0.510 0.128 DV7CK = 0 DV1CK = 1 Maximum Time Setting [ms] 65.3 4.1 1.0 0.255 DV1CK = 0 Maximum Time Setting [ms] 62.2 2.0 0.510 0.128 DV7CK = 1 DV1CK = 1 Maximum Time Setting [ms] 62.2 4.1 1.0 0.255 Maximum Time Setting [ms] 62.2 - - - SLOW1/2, SLEEP1/2 Mode Resolution [s] Resolution [s] Resolution [s] Resolution [s] Resolution [s] 000 001 010 011 128.0 8.0 2.0 0.5 256.0 16.0 4.0 1.0 244.14 8.0 2.0 0.5 244.14 16.0 4.0 1.0 244.14 - - - Page 124 TMP86FS64FG 12.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC5 pin. When a match between the up-counter and the TC5DR value is detected, an INTTC5 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC5 pin. Since a match is detected at the falling edge of the input pulse to the TC5 pin, the INTTC5 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC5DR. The minimum pulse width applied to the TC5 pin are shown in Table 12-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not supplied in these modes. Table 12-2 External Source Clock for TimerCounter 5 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 23/fc 23/fc Page 125 12. 8-Bit TimerCounter 5 (TC5) 12.1 Configuration TMP86FS64FG 12.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC5DR value is detected, the logic level output from the PDO5 pin is switched to the opposite state and INTTC5 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC5DR value is detected, the logic level output from the PDO5 pin is switched to the opposite state again and INTTC5 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO5 pin is high. Therefore, if the timer is stopped when the PDO5 pin is low, the duty pulse may be shorter than the programmed value. Example :Generating 1024 Hz pulse (fc = 16.0 Mhz) LD LD LD (TC5CR), 00000110B (TC5DR), 3DH (TC5CR), 00100110B : Sets the PDO mode. (TC5M = 10, TC5CK = 001) : 1/1024 / 27/fc / 2 (half cycle period) = 3DH : Start TC5 Internal clock Counter TC5DR Timer F/F 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 n Match detect PDO5 pin INTTC5 interrupt request Figure 12-2 PDO Mode Timing Chart Page 126 TMP86FS64FG 12.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC5DR value is detected, the logic level output from the PWM5 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM5 pin becomes high. The INTTC5 interrupt request is generated at this time. When the timer is stopped, the PWM5 pin is high. Therefore, if the timer is stopped when the PWM5 pin is low, one PMW cycle may be shorter than the programmed value. TC5DR is serially connected to the shift register. If TC5DR is programmed during PWM output, the data set to TC5DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC5DR is shifted when the timer is started by setting TC5CR Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes. Note 2: In the PWM output mode, program TC5DR immediately after the INTTC5 interrupt request is generated (typically in the INTTC5 interrupt service routine.) When the programming of TC5DR and the INTTC5 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC5 interrupt request is issued. TC5CR Internal clock Counter TC5DR 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite ? n m Rewrite p Rewrite Data shift m Data shift Shift register Timer F/F ? n Data shift Match detect Match detect Match detect PWM5 pin INTTC5 interrupt request n n m PWM cycle Figure 12-3 PWM output Mode Timing Chart (TC5) Page 127 12. 8-Bit TimerCounter 5 (TC5) 12.1 Configuration TMP86FS64FG Table 12-3 PWM Mode (Example: fc = 16 MHz) NORMAL1/2, IDLE1/2 Mode TC5CK DV1CK = 0 Resolution [ns] 000 001 010 011 100 101 110 - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 0 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - DV1CK = 0 Resolution [ns] - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 1 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - Page 128 TMP86FS64FG 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TC6S fc/211, fc212 or fs/23 fc/27, fc28 fc/25, fc26 fc/23, fc24 fc/22, fc23 fc/2, fc22 fc, fc/2 (Note) A B Source C Clock Clear D EY Y 8-bit up-counter F G H S 3 CMP Overflow detect 0 1 Match detect S Y TC6 pin Timer F/F TC6CK Toggle Port (Note) TC6S TC6M 2 0 Y 1 Clear S PWM output mode PWM6/ PDO6/ pin TC6CR TC6DR TC6S INTTC6 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 13-1 TimerCounter 6 (TC6) Page 129 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TMP86FS64FG 13.2 TimerCounter Control The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and timer registers 6 (TC6DR). Timer Register and Control Register TC6DR (0017) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC6CR (0016) 7 6 5 TC6S 4 3 TC6CK 2 1 TC6M 0 Read/Write (Initial value: **00 0000) TC6S TC6 start control 0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 000 001 fc/211 fc/27 fc/25 fc/2 3 R/W SLOW1/2, SLEEP1/2 mode fs/23 - - - - - - R/W DV7CK = 1 DV1CK = 0 fs/23 fc/27 fc/25 fc/2 3 Divider DV1CK = 1 fc/212 fc/28 fc/26 fc/2 4 DV1CK = 1 fs/23 fc/28 fc/26 fc/2 4 DV9 DV5 DV3 DV1 - - - TC6CK TC6 source clock select [Hz] 010 011 100 101 110 111 fc/22 fc/2 fc fc/23 fc/22 fc/2 fc/22 fc/2 fc fc/23 fc/22 fc/2 External clock (TC6 pin input) TC6M TC6 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: To set the timer registers, the following relationship must be satisfied. 1 TC6DR 255 Note 3: To start timer operation (TC6S = 0 1) or disable timer operation (TC6S = 1 0), do not change the TC6CR Timer Mode 000 001 010 TC6CK 011 100 101 110 111 O O O O - - - - Event Counter Mode - - - - - - - O PDO Mode O O O - - - - - PWM Mode - - - O O O O x Page 130 TMP86FS64FG Note: O : Available source clock Page 131 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TMP86FS64FG 13.3 Function TimerCounter 6 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 13.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC6DR value is detected, an INTTC6 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 13-1 Source Clock for TimerCounter 6 (Example: fc = 16 MHz, fs = 32.768 kHz) NORMAL1/2, IDLE1/2 Mode TC6CK DV1CK = 0 Maximum Time Setting [ms] 32.6 2.0 0.510 0.128 DV7CK = 0 DV1CK = 1 Maximum Time Setting [ms] 65.3 4.1 1.0 0.255 DV1CK = 0 Maximum Time Setting [ms] 62.2 2.0 0.510 0.128 DV7CK = 1 DV1CK = 1 Maximum Time Setting [ms] 62.2 4.1 1.0 0.255 Maximum Time Setting [ms] 62.2 - - - SLOW1/2, SLEEP1/2 Mode Resolution [s] Resolution [s] Resolution [s] Resolution [s] Resolution [s] 000 001 010 011 128.0 8.0 2.0 0.5 256.0 16.0 4.0 1.0 244.14 8.0 2.0 0.5 244.14 16.0 4.0 1.0 244.14 - - - Page 132 TMP86FS64FG 13.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC6 pin. When a match between the up-counter and the TC6DR value is detected, an INTTC6 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC6 pin. Since a match is detected at the falling edge of the input pulse to the TC6 pin, the INTTC6 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC6DR. The minimum pulse width applied to the TC6 pin are shown in Table 13-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not supplied in these modes. Table 13-2 External Source Clock for TimerCounter 6 Minimum Pulse Width NORMAL1/2, IDLE1/2 mode High-going Low-going 23/fc 23/fc Page 133 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TMP86FS64FG 13.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC6DR value is detected, the logic level output from the PDO6 pin is switched to the opposite state and INTTC6 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC6DR value is detected, the logic level output from the PDO6 pin is switched to the opposite state again and INTTC6 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO6 pin is high. Therefore, if the timer is stopped when the PDO6 pin is low, the duty pulse may be shorter than the programmed value. Example :Generating 1024 Hz pulse (fc = 16.0 Mhz) LD LD LD (TC6CR), 00000110B (TC6DR), 3DH (TC6CR), 00100110B : Sets the PDO mode. (TC6M = 10, TC6CK = 001) : 1/1024 / 27/fc / 2 (half cycle period) = 3DH : Start TC6 Internal clock Counter TC6DR Timer F/F 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 n Match detect PDO6 pin INTTC6 interrupt request Figure 13-2 PDO Mode Timing Chart Page 134 TMP86FS64FG 13.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC6DR value is detected, the logic level output from the PWM6 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM6 pin becomes high. The INTTC6 interrupt request is generated at this time. When the timer is stopped, the PWM6 pin is high. Therefore, if the timer is stopped when the PWM6 pin is low, one PMW cycle may be shorter than the programmed value. TC6DR is serially connected to the shift register. If TC6DR is programmed during PWM output, the data set to TC6DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC6DR is shifted when the timer is started by setting TC6CR Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes. Note 2: In the PWM output mode, program TC6DR immediately after the INTTC6 interrupt request is generated (typically in the INTTC6 interrupt service routine.) When the programming of TC6DR and the INTTC6 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is issued. TC6CR Internal clock Counter TC6DR 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite ? n m Rewrite p Rewrite Data shift m Data shift Shift register Timer F/F ? n Data shift Match detect Match detect Match detect PWM6 pin INTTC6 interrupt request n n m PWM cycle Figure 13-3 PWM output Mode Timing Chart (TC6) Page 135 13. 8-Bit TimerCounter 6 (TC6) 13.1 Configuration TMP86FS64FG Table 13-3 PWM Mode (Example: fc = 16 MHz) NORMAL1/2, IDLE1/2 Mode TC6CK DV1CK = 0 Resolution [ns] 000 001 010 011 100 101 110 - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 0 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - DV1CK = 0 Resolution [ns] - - - 500 250 125 - Cycle [s] - - - 128 64 32 - DV7CK = 1 DV1CK = 1 Resolution [ns] - - - 1000 500 250 - Cycle [s] - - - 256 128 64 - Page 136 TMP86FS64FG 14. Asynchronous Serial interface (UART ) 14.1 Configuration UART control register 1 UARTCR1 Transmit data buffer TDBUF Receive data buffer RDBUF 3 2 Receive control circuit Transmit control circuit 2 Shift register Shift register Parity bit Stop bit Noise rejection circuit M P X M P X INTTRX RXD1 RXD2 TXD1 TXD2 INTTRX IrDA control Transmit/receive clock IRDACR IrDA output control register Y S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC4 fc/96 A B C D E F G H M P X A B C S 2 fc/26 7 fc/2 fc/28 2 Y Counter UARTSR 4 UARTCR2 SCISEL UART pin select register MPX: Multiplexer UART status register Baud rate generator UART control register 2 Figure 14-1 UART (Asynchronous Serial Interface) Page 137 14. Asynchronous Serial interface (UART ) 14.2 Control TMP86FS64FG 14.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR). TXD1 pin and RXD1 pin can be selected a port assignment by UART Pin Select Register (SCISEL). And Infrared data format (IrDA) output is available by setting IrDA output control register (IRDACR) through TXD1 pin. UART Control Register1 UARTCR1 (001BH) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC4 ( Input INTTC4) fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UARTCR1 UART Control Register2 UARTCR2 (001CH) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UARTCR2 Page 138 TMP86FS64FG UART Status Register UARTSR (001BH) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Receive Data Buffer RDBUF (001DH) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (001DH) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) UART Pin Select Register SCISEL (002AH) 7 6 5 4 3 2 TXD SEL 1 RXD SEL 0 (Initial value: **** *00*) TXDESEL RXDSEL TXD connect pin select RXD connect pin select 0: 1: 0: 1: P41 P44 P42 P45 R/W Note 1: Do not change SCISEL register during UART operation. Note 2: Set SCISEL register before performing the setting terminal of a I/O port when changing a terminal. Page 139 14. Asynchronous Serial interface (UART ) 14.3 Transfer Data Format TMP86FS64FG 14.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1 PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 14-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 14-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 14-3 sequence except for the initial setting. Page 140 TMP86FS64FG 14.4 Infrared (IrDA) Data Format Transfer Mode Infrared data format (IrDA) output is available by setting IrDA output control register (IRDACR) through TXD1 pin. IrDA Output Control Register IRDACR (001AH) 7 6 5 4 3 2 1 0 IRDA SEL (Initial value: **** ***0) IRDASEL IrDA output / UART output select 0: 1: UART output IrDA output R/W Start bit UART output IrDA output D0 D1 D2 D7 Stop bit 3/16 bit width Figure 14-4 Example of Infrared Data Format (Comparison of Normal output and IrDA output) Page 141 14. Asynchronous Serial interface (UART ) 14.5 Transfer Rate TMP86FS64FG 14.5 Transfer Rate The baud rate of UART is set of UARTCR1 Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 4 MHz 19200 [baud] 9600 4800 2400 1200 600 When TC4 is used as the UART transfer rate (when UARTCR1 14.6 Data Sampling Method The UART receiver keeps sampling input using the clock selected by UARTCR1 RXD1 pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD1 pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 14-5 Data Sampling Method Page 142 TMP86FS64FG 14.7 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1 14.8 Parity Set parity / no parity by UARTCR1 14.9 Transmit/Receive Operation 14.9.1 Data Transmit Operation Set UARTCR1 14.9.2 Data Receive Operation Set UARTCR1 Note:When a receive operation is disabled by setting UARTCR1 Page 143 14. Asynchronous Serial interface (UART ) 14.10 Status Flag TMP86FS64FG 14.10Status Flag 14.10.1Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR RXD1 pin Parity Stop Shift register UARTSR xxxx0** pxxxx0* 1pxxxx0 After reading UARTSR then RDBUF clears PERR. INTTRX interrupt Figure 14-6 Generation of Parity Error 14.10.2Framing Error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR RXD1 pin Final bit Stop Shift register UARTSR xxx0** xxxx0* 0xxxx0 After reading UARTSR then RDBUF clears FERR. INTTRX interrupt Figure 14-7 Generation of Framing Error 14.10.3Overrun Error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR Page 144 TMP86FS64FG UARTSR RXD1 pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 UARTSR After reading UARTSR then RDBUF clears OERR. INTTRX interrupt Figure 14-8 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR 14.10.4Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR RXD1 pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 xxxx After reading UARTSR then RDBUF clears RBFL. UARTSR INTTRX interrupt Figure 14-9 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR 14.10.5Transmit Data Buffer Empty When no data is in the transmit buffer TDBUF, UARTSR Page 145 14. Asynchronous Serial interface (UART ) 14.10 Status Flag TMP86FS64FG Data write TDBUF Data write xxxx yyyy zzzz Shift register TXD1 pin *****1 1xxxx0 *1xxxx Bit 0 ****1x Final bit *****1 Stop 1yyyy0 Start UARTSR INTTRX interrupt Figure 14-10 Generation of Transmit Data Buffer Empty 14.10.6Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR Shift register TXD1 pin ***1xx ****1x *****1 1yyyy0 *1yyyy Stop Data write for TDBUF Start Bit 0 UARTSR UARTSR INTTRX interrupt Figure 14-11 Generation of Transmit End Flag and Transmit Data Buffer Empty Page 146 TMP86FS64FG 15. Synchronous Serial Interface (SIO1) The TMP86FS64FG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO1, SI1, SCK1 port. 15.1 Configuration SIO control / status register SIO1SR SIO1CR1 SIO1CR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO1 Serial data output 8-bit transfer 4-bit transfer SI1 Serial data input INTSIO1 interrupt request Serial clock SCK1 Serial clock I/O Figure 15-1 Serial Interface Page 147 15. Synchronous Serial Interface (SIO1) 15.2 Control TMP86FS64FG 15.2 Control The serial interface is controlled by SIO control registers (SIO1CR1/SIO1CR2). The serial interface status can be determined by reading SIO status register (SIO1SR). The transmit and receive data buffer is controlled by the SIO1CR2 SIO1CR1 (0028H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) SIOS Indicate transfer start / stop 0: 1: 0: 1: 000: 010: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Except the above: Reserved NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 SLOW1/2 SLEEP1/2 mode fs/25 Write only Write only SIOINH Continue / abort transfer SIOM Transfer mode select 100: 101: 110: DV1CK = 0 DV1CK = 1 DV1CK = 1 DV1CK = 1 000 001 SCK Serial clock select 010 011 100 101 110 111 fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 fc/214 fc/29 fc/28 fc/27 fc/26 fc/25 fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 Reserved External clock (Input from SCK1 pin ) fs/25 fc/29 fc/28 fc/27 fc/26 fc/25 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz] Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock. Note 3: SIO1CR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Control Register 2 SIO1CR2 (0029H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 148 TMP86FS64FG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 0F90H 0F90H ~ 0F91H 0F90H ~ 0F92H 0F90H ~ 0F93H 0F90H ~ 0F94H 0F90H ~ 0F95H 0F90H ~ 0F96H 0F90H ~ 0F97H Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 0F90H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIO1CR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIO1CR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Status Register SIO1SR (0029H) 7 SIOF 6 SEF 5 4 3 2 1 0 SIOF SEF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only Note 1: Tf; Frame time, TD; Data transfer time Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1". (output) SCK1 output TD Tf Figure 15-2 Frame time (Tf) and Data transfer time (TD) 15.3 Serial clock 15.3.1 Clock source Internal clock or external clock for the source clock is selected by SIO1CR1 Page 149 15. Synchronous Serial Interface (SIO1) 15.3 Serial clock TMP86FS64FG 15.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK1 pin. The SCK1 pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 15-1 Serial Clock Rate NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 SCK 000 Clock fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 1.91 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External DV1CK = 1 Clock fc/214 fc/29 fc/28 fc/27 fc/26 fc/25 External Baud Rate 0.95 Kbps 30.52 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps External DV1CK = 0 Clock fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 1024 bps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External DV7CK = 1 DV1CK = 1 Clock fs/25 fc/29 fc/28 fc/27 fc/26 fc/25 External Baud Rate 1024 bps 30.52 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps External Clock fs/25 Baud Rate 1024 bps SLOW1/2, SLEEP1/2 mode 001 010 - - 011 - - 100 - - 101 110 111 External External Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz) Automatically wait function SCK1 pin (output) SO1 pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 15-3 Automatic Wait Function (at 4-bit transmit mode) 15.3.1.2 External clock An external clock connected to the SCK1 pin is used as the serial clock. In this case, output latch of this port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz). Page 150 TMP86FS64FG SCK1 pin (Output) tSCKL tSCKH tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes) 4/fs (In the SLOW1/2, SLEEP1/2 modes) tSCKL, tSCKH > 4tcyc Figure 15-4 External clock pulse width 15.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 15.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK1 pin input/ output). 15.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK1 pin input/output). SCK1 pin SO1 pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK1 pin SI1 pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don't care (b) Trailing edge Figure 15-5 Shift edge 15.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 15.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIO1CR2 15. Synchronous Serial Interface (SIO1) 15.6 Transfer Mode TMP86FS64FG An INTSIO1 interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. The number of words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not required to be stopped. SCK1 pin SO1 pin a0 a1 a2 a3 INTSIO1 interrupt (a) 1 word transmit SCK1 pin SO1 pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO1 interrupt (b) 3 words transmit SCK1 pin SI1 pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO1 interrupt (c) 3 words receive Figure 15-6 Number of words to transfer (Example: 1word = 4bit) 15.6 Transfer Mode SIO1CR1 15.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIO1CR1 Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. Page 152 TMP86FS64FG When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIO1CR1 |